src/soc/alu/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.alu.pipeline import ALUBasePipe
  16 from soc.alu.alu_input_record import CompALUOpSubset
  17 from soc.alu.pipe_data import ALUPipeSpec
  18 import random
  19
  20 class TestCase:
  21     def __init__(self, program, regs, sprs, name):
  22         self.program = program
  23         self.regs = regs
  24         self.sprs = sprs
  25         self.name = name
  26
  27 def get_rec_width(rec):
  28     recwidth = 0
  29     # Setup random inputs for dut.op
  30     for p in rec.ports():
  31         width = p.width
  32         recwidth += width
  33     return recwidth
  34
  35 def set_alu_inputs(alu, dec2, sim):
  36     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  37     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  38     # and place it into data_i.b
  39
  40     reg3_ok = yield dec2.e.read_reg3.ok
  41     reg1_ok = yield dec2.e.read_reg1.ok
  42     assert reg3_ok != reg1_ok
  43     if reg3_ok:
  44         data1 = yield dec2.e.read_reg3.data
  45         data1 = sim.gpr(data1).value
  46     elif reg1_ok:
  47         data1 = yield dec2.e.read_reg1.data
  48         data1 = sim.gpr(data1).value
  49     else:
  50         data1 = 0
  51
  52     yield alu.p.data_i.a.eq(data1)
  53
  54     # If there's an immediate, set the B operand to that
  55     reg2_ok = yield dec2.e.read_reg2.ok
  56     imm_ok = yield dec2.e.imm_data.imm_ok
  57     if imm_ok:
  58         data2 = yield dec2.e.imm_data.imm
  59     elif reg2_ok:
  60         data2 = yield dec2.e.read_reg2.data
  61         data2 = sim.gpr(data2).value
  62     else:
  63         data2 = 0
  64     yield alu.p.data_i.b.eq(data2)
  65
  66
  67
  68 def set_extra_alu_inputs(alu, dec2, sim):
  69     carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  70     yield alu.p.data_i.carry_in.eq(carry)
  71     so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  72     yield alu.p.data_i.so.eq(so)
  73
  74
  75 # This test bench is a bit different than is usual. Initially when I
  76 # was writing it, I had all of the tests call a function to create a
  77 # device under test and simulator, initialize the dut, run the
  78 # simulation for ~2 cycles, and assert that the dut output what it
  79 # should have. However, this was really slow, since it needed to
  80 # create and tear down the dut and simulator for every test case.
  81
  82 # Now, instead of doing that, every test case in ALUTestCase puts some
  83 # data into the test_data list below, describing the instructions to
  84 # be tested and the initial state. Once all the tests have been run,
  85 # test_data gets passed to TestRunner which then sets up the DUT and
  86 # simulator once, runs all the data through it, and asserts that the
  87 # results match the pseudocode sim at every cycle.
  88
  89 # By doing this, I've reduced the time it takes to run the test suite
  90 # massively. Before, it took around 1 minute on my computer, now it
  91 # takes around 3 seconds
  92
  93 test_data = []
  94
  95
  96 class ALUTestCase(FHDLTestCase):
  97     def __init__(self, name):
  98         super().__init__(name)
  99         self.test_name = name
 100     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
 101         tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
 102         test_data.append(tc)
 103
 104     def test_rand(self):
 105         insns = ["add", "add.", "and", "or", "xor", "subf"]
 106         for i in range(40):
 107             choice = random.choice(insns)
 108             lst = [f"{choice} 3, 1, 2"]
 109             initial_regs = [0] * 32
 110             initial_regs[1] = random.randint(0, (1<<64)-1)
 111             initial_regs[2] = random.randint(0, (1<<64)-1)
 112             self.run_tst_program(Program(lst), initial_regs)
 113
 114     def test_rand_imm(self):
 115         insns = ["addi", "addis", "subfic"]
 116         for i in range(10):
 117             choice = random.choice(insns)
 118             imm = random.randint(-(1<<15), (1<<15)-1)
 119             lst = [f"{choice} 3, 1, {imm}"]
 120             print(lst)
 121             initial_regs = [0] * 32
 122             initial_regs[1] = random.randint(0, (1<<64)-1)
 123             self.run_tst_program(Program(lst), initial_regs)
 124
 125     def test_rand_imm_logical(self):
 126         insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
 127         for i in range(10):
 128             choice = random.choice(insns)
 129             imm = random.randint(0, (1<<16)-1)
 130             lst = [f"{choice} 3, 1, {imm}"]
 131             print(lst)
 132             initial_regs = [0] * 32
 133             initial_regs[1] = random.randint(0, (1<<64)-1)
 134             self.run_tst_program(Program(lst), initial_regs)
 135
 136     def test_adde(self):
 137         lst = ["adde. 5, 6, 7"]
 138         initial_regs = [0] * 32
 139         initial_regs[6] = random.randint(0, (1<<64)-1)
 140         initial_regs[7] = random.randint(0, (1<<64)-1)
 141         initial_sprs = {}
 142         xer = SelectableInt(0, 64)
 143         xer[XER_bits['CA']] = 1
 144         initial_sprs[special_sprs['XER']] = xer
 145         self.run_tst_program(Program(lst), initial_regs, initial_sprs)
 146
 147     def test_ilang(self):
 148         rec = CompALUOpSubset()
 149
 150         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
 151         alu = ALUBasePipe(pspec)
 152         vl = rtlil.convert(alu, ports=[])
 153         with open("pipeline.il", "w") as f:
 154             f.write(vl)
 155
 156
 157 class TestRunner(FHDLTestCase):
 158     def __init__(self, test_data):
 159         super().__init__("run_all")
 160         self.test_data = test_data
 161
 162     def run_all(self):
 163         m = Module()
 164         comb = m.d.comb
 165         instruction = Signal(32)
 166
 167         pdecode = create_pdecode()
 168
 169         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 170
 171         rec = CompALUOpSubset()
 172
 173         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
 174         m.submodules.alu = alu = ALUBasePipe(pspec)
 175
 176         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 177         comb += alu.p.valid_i.eq(1)
 178         comb += alu.n.ready_i.eq(1)
 179         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 180         sim = Simulator(m)
 181
 182         sim.add_clock(1e-6)
 183         def process():
 184             for test in self.test_data:
 185                 print(test.name)
 186                 program = test.program
 187                 self.subTest(test.name)
 188                 simulator = ISA(pdecode2, test.regs, test.sprs)
 189                 gen = program.generate_instructions()
 190                 instructions = list(zip(gen, program.assembly.splitlines()))
 191
 192                 index = simulator.pc.CIA.value//4
 193                 while index < len(instructions):
 194                     ins, code = instructions[index]
 195
 196                     print("0x{:X}".format(ins & 0xffffffff))
 197                     print(code)
 198
 199                     # ask the decoder to decode this binary data (endian'd)
 200                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 201                     yield instruction.eq(ins)          # raw binary instr.
 202                     yield Settle()
 203                     yield from set_alu_inputs(alu, pdecode2, simulator)
 204                     yield from set_extra_alu_inputs(alu, pdecode2, simulator)
 205                     yield
 206                     opname = code.split(' ')[0]
 207                     yield from simulator.call(opname)
 208                     index = simulator.pc.CIA.value//4
 209
 210                     vld = yield alu.n.valid_o
 211                     while not vld:
 212                         yield
 213                         vld = yield alu.n.valid_o
 214                     yield
 215                     alu_out = yield alu.n.data_o.o
 216                     out_reg_valid = yield pdecode2.e.write_reg.ok
 217                     if out_reg_valid:
 218                         write_reg_idx = yield pdecode2.e.write_reg.data
 219                         expected = simulator.gpr(write_reg_idx).value
 220                         print(f"expected {expected:x}, actual: {alu_out:x}")
 221                         self.assertEqual(expected, alu_out)
 222                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 223                                                             simulator)
 224
 225         sim.add_sync_process(process)
 226         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 227                             traces=[]):
 228             sim.run()
 229     def check_extra_alu_outputs(self, alu, dec2, sim):
 230         rc = yield dec2.e.rc.data
 231         if rc:
 232             cr_expected = sim.crl[0].get_range().value
 233             cr_actual = yield alu.n.data_o.cr0
 234             self.assertEqual(cr_expected, cr_actual)
 235
 236
 237 if __name__ == "__main__":
 238     unittest.main(exit=False)
 239     suite = unittest.TestSuite()
 240     suite.addTest(TestRunner(test_data))
 241
 242     runner = unittest.TextTestRunner()
 243     runner.run(suite)