src/soc/bus/test/test_minerva.py

   1 from nmigen_soc.wishbone.sram import SRAM
   2 from nmigen import Memory, Signal, Module
   3 from soc.minerva.units.loadstore import BareLoadStoreUnit, CachedLoadStoreUnit
   4
   5
   6 class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
   7     def __init__(self, addr_wid=64, mask_wid=4, data_wid=64):
   8         super().__init__(addr_wid, mask_wid, data_wid)
   9
  10     def elaborate(self, platform):
  11         m = super().elaborate(platform)
  12         comb = m.d.comb
  13         # small 32-entry Memory
  14         memory = Memory(width=self.addr_wid, depth=32)
  15         m.submodules.sram = sram = SRAM(memory=memory, granularity=8,
  16                                         features={'cti', 'bte', 'err'})
  17         dbus = self.dbus
  18
  19         # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
  20         # note: SRAM is a target (slave), dbus is initiator (master)
  21         fanouts = ['adr', 'dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
  22         fanins = ['dat_r', 'ack', 'err']
  23         for fanout in fanouts:
  24             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
  25         for fanin in fanins:
  26             comb += getattr(dbus, fanin).eq(getattr(sram.bus, fanin))
  27
  28         return m