src/soc/bus/test/test_minerva.py

   1 from nmigen_soc.wishbone.sram import SRAM
   2 from nmigen import Memory, Signal, Module
   3 from soc.minerva.units.loadstore import BareLoadStoreUnit, CachedLoadStoreUnit
   4 from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit
   5
   6
   7 class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
   8     def __init__(self, pspec):
   9         super().__init__(pspec)
  10         # small 32-entry Memory
  11         if (hasattr(pspec, "dmem_test_depth") and
  12             isinstance(pspec.dmem_test_depth, int)):
  13             depth = pspec.dmem_test_depth
  14         else:
  15             depth = 32
  16         print ("TestSRAMBareLoadStoreUnit depth", depth)
  17
  18         self.mem = Memory(width=self.data_wid, depth=depth)
  19
  20     def elaborate(self, platform):
  21         m = super().elaborate(platform)
  22         comb = m.d.comb
  23         m.submodules.sram = sram = SRAM(memory=self.mem, granularity=8,
  24                                         features={'cti', 'bte', 'err'})
  25         dbus = self.dbus
  26
  27         # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
  28         # note: SRAM is a target (slave), dbus is initiator (master)
  29         fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
  30         fanins = ['dat_r', 'ack', 'err']
  31         for fanout in fanouts:
  32             print ("fanout", fanout, getattr(sram.bus, fanout).shape(),
  33                                      getattr(dbus, fanout).shape())
  34             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
  35             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
  36         for fanin in fanins:
  37             comb += getattr(dbus, fanin).eq(getattr(sram.bus, fanin))
  38         # connect address
  39         comb += sram.bus.adr.eq(dbus.adr)
  40
  41         return m
  42
  43
  44 class TestSRAMBareFetchUnit(BareFetchUnit):
  45     def __init__(self, pspec):
  46         super().__init__(pspec)
  47         # default: small 32-entry Memory
  48         if (hasattr(pspec, "imem_test_depth") and
  49             isinstance(pspec.imem_test_depth, int)):
  50             depth = pspec.imem_test_depth
  51         else:
  52             depth = 32
  53         print ("TestSRAMBareFetchUnit depth", depth)
  54         self.mem = Memory(width=self.data_wid, depth=depth)
  55
  56     def _get_memory(self):
  57         return self.mem
  58
  59     def elaborate(self, platform):
  60         m = super().elaborate(platform)
  61         comb = m.d.comb
  62         m.submodules.sram = sram = SRAM(memory=self.mem, read_only=True,
  63                                         features={'cti', 'bte', 'err'})
  64         ibus = self.ibus
  65
  66         # directly connect the wishbone bus of FetchUnitInterface to SRAM
  67         # note: SRAM is a target (slave), ibus is initiator (master)
  68         fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
  69         fanins = ['dat_r', 'ack', 'err']
  70         for fanout in fanouts:
  71             print ("fanout", fanout, getattr(sram.bus, fanout).shape(),
  72                                      getattr(ibus, fanout).shape())
  73             comb += getattr(sram.bus, fanout).eq(getattr(ibus, fanout))
  74             comb += getattr(sram.bus, fanout).eq(getattr(ibus, fanout))
  75         for fanin in fanins:
  76             comb += getattr(ibus, fanin).eq(getattr(sram.bus, fanin))
  77         # connect address
  78         comb += sram.bus.adr.eq(ibus.adr)
  79
  80         return m