1 """demonstration of nmigen-soc SRAM behind a wishbone bus
3 * https://bugs.libre-soc.org/show_bug.cgi?id=382
5 from nmigen_soc
.wishbone
.sram
import SRAM
6 from nmigen
import Memory
, Signal
, Module
8 memory
= Memory(width
=64, depth
=16)
9 sram
= SRAM(memory
=memory
, granularity
=16)
11 # valid wishbone signals include
22 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
24 m
.submodules
.sram
= sram
28 def print_sig(sig
, format
=None):
30 print(f
"{sig.__repr__()} = {(yield sig)}")
32 print(f
"{sig.__repr__()} = {hex((yield sig))}")
35 # enable necessary signals for write
37 yield sram
.bus
.sel
[en
].eq(1)
38 yield sram
.bus
.we
.eq(1)
39 yield sram
.bus
.cyc
.eq(1)
40 yield sram
.bus
.stb
.eq(1)
42 # put data and address on bus
43 yield sram
.bus
.adr
.eq(0x4)
44 yield sram
.bus
.dat_w
.eq(0xdeadbeef)
47 # set necessary signal to read bus
49 yield sram
.bus
.we
.eq(0)
50 yield sram
.bus
.adr
.eq(0)
51 yield sram
.bus
.cyc
.eq(1)
52 yield sram
.bus
.stb
.eq(1)
55 # see sync_behaviors.py
56 # for why we need Settle()
57 # debug print the bus address/data
59 yield from print_sig(sram
.bus
.adr
)
60 yield from print_sig(sram
.bus
.dat_r
, "h")
63 data
= yield sram
.bus
.dat_r
66 # set necessary signal to read bus
68 yield sram
.bus
.we
.eq(0)
69 yield sram
.bus
.adr
.eq(0x4)
70 yield sram
.bus
.cyc
.eq(1)
71 yield sram
.bus
.stb
.eq(1)
74 # see sync_behaviors.py
75 # for why we need Settle()
76 # debug print the bus address/data
78 yield from print_sig(sram
.bus
.adr
)
79 yield from print_sig(sram
.bus
.dat_r
, "h")
82 data
= yield sram
.bus
.dat_r
83 assert data
== 0xdeadbeef
86 yield sram
.bus
.cyc
.eq(0)
87 yield sram
.bus
.stb
.eq(0)
90 sim_writer
= sim
.write_vcd(f
"{__file__[:-3]}.vcd")
93 sim
.add_sync_process(process
)