src/soc/clock/select.py

   1 """Clock selection.
   2 """
   3
   4 from nmigen import (Module, Array, Signal, Mux, Elaboratable, ClockSignal,
   5                     ResetSignal)
   6 from nmigen.cli import rtlil
   7
   8
   9 class ClockSelect(Elaboratable):
  10     def __init__(self):
  11
  12         self.clk_sel_i = Signal() # clock source selection
  13         self.clk_24_i = Signal(reset_less=True) # 24 mhz external incoming
  14         self.pll_clk_i = Signal(reset_less=True)  # PLL input
  15         self.core_clk_o = Signal(reset_less=True) # main core clock (selectable)
  16
  17     def elaborate(self, platform):
  18         m = Module()
  19         comb, sync = m.d.comb, m.d.sync
  20
  21         # set up system, zero and one clocks
  22         comb += self.core_clk_o.eq(Mux(self.clk_sel_i,
  23                                        self.pll_clk_i, self.clk_24_i))
  24
  25         return m
  26
  27     def ports(self):
  28         return [self.clk_24_i, self.pll_18_o, self.clk_sel_i, self.core_clk_o]
  29
  30
  31 if __name__ == '__main__':
  32     dut = ClockSelect()
  33
  34     vl = rtlil.convert(dut, ports=dut.ports())
  35     with open("test_clk_sel.il", "w") as f:
  36         f.write(vl)
  37