1 from nmigen
import Signal
, Module
, Record
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.compat
.sim
import run_simulation
, Settle
4 from nmutil
.formaltest
import FHDLTestCase
5 from nmigen
.cli
import rtlil
7 from soc
.config
.test
.test_loadstore
import TestMemPspec
8 from soc
.config
.loadstore
import ConfigMemoryPortInterface
11 def wait_busy(port
, no
=False,debug
=None):
14 busy
= yield port
.busy_o
15 print("busy", no
, busy
, cnt
, debug
)
22 def wait_addr(port
,debug
=None):
25 addr_ok
= yield port
.addr_ok_o
26 print("addrok", addr_ok
,cnt
,debug
)
36 ldok
= yield port
.ld
.ok
37 exc_happened
= yield port
.exc_o
.happened
38 print("ldok", ldok
, "exception", exc_happened
, "count", cnt
)
40 if ldok
or exc_happened
:
45 def pi_st(port1
, addr
, data
, datalen
, msr_pr
=0, is_dcbz
=0):
47 # have to wait until not busy
48 yield from wait_busy(port1
,debug
="pi_st_A") # wait while busy
50 # set up a ST on the port. address first:
51 yield port1
.is_dcbz_i
.eq(is_dcbz
) # reset dcbz too
52 yield port1
.is_st_i
.eq(1) # indicate ST
53 yield port1
.data_len
.eq(datalen
) # ST length (1/2/4/8)
54 yield port1
.msr_pr
.eq(msr_pr
) # MSR PR bit (1==>virt, 0==>real)
56 yield port1
.addr
.data
.eq(addr
) # set address
57 yield port1
.addr
.ok
.eq(1) # set ok
59 yield from wait_addr(port1
) # wait until addr ok
60 # yield # not needed, just for checking
61 # yield # not needed, just for checking
62 # assert "ST" for one cycle (required by the API)
63 yield port1
.st
.data
.eq(data
)
64 yield port1
.st
.ok
.eq(1)
66 yield port1
.st
.ok
.eq(0)
67 yield from wait_busy(port1
,debug
="pi_st_E") # wait while busy
69 # can go straight to reset.
70 yield port1
.is_st_i
.eq(0) # end
71 yield port1
.addr
.ok
.eq(0) # set !ok
72 yield port1
.is_dcbz_i
.eq(0) # reset dcbz too
75 # copy of pi_st removed
77 def pi_ld(port1
, addr
, datalen
, msr_pr
=0):
79 # have to wait until not busy
80 yield from wait_busy(port1
,debug
="pi_ld_A") # wait while busy
82 # set up a LD on the port. address first:
83 yield port1
.is_ld_i
.eq(1) # indicate LD
84 yield port1
.data_len
.eq(datalen
) # LD length (1/2/4/8)
85 yield port1
.msr_pr
.eq(msr_pr
) # MSR PR bit (1==>virt, 0==>real)
87 yield port1
.addr
.data
.eq(addr
) # set address
88 yield port1
.addr
.ok
.eq(1) # set ok
90 yield from wait_addr(port1
) # wait until addr ok
92 yield from wait_ldok(port1
) # wait until ld ok
93 data
= yield port1
.ld
.data
94 exc_happened
= yield port1
.exc_o
.happened
97 yield port1
.is_ld_i
.eq(0) # end
98 yield port1
.addr
.ok
.eq(0) # set !ok
102 yield from wait_busy(port1
,debug
="pi_ld_E") # wait while busy
107 def pi_ldst(arg
, dut
, msr_pr
=0):
109 # do two half-word stores at consecutive addresses, then two loads
115 yield from pi_st(dut
, addr1
, data
, 2, msr_pr
)
116 yield from pi_st(dut
, addr2
, data2
, 2, msr_pr
)
117 result
= yield from pi_ld(dut
, addr1
, 2, msr_pr
)
118 result2
= yield from pi_ld(dut
, addr2
, 2, msr_pr
)
119 arg
.assertEqual(data
, result
, "data %x != %x" % (result
, data
))
120 arg
.assertEqual(data2
, result2
, "data2 %x != %x" % (result2
, data2
))
122 # now load both in a 32-bit load to make sure they're really consecutive
123 data3
= data |
(data2
<< 16)
124 result3
= yield from pi_ld(dut
, addr1
, 4, msr_pr
)
125 arg
.assertEqual(data3
, result3
, "data3 %x != %x" % (result3
, data3
))
128 def tst_config_pi(testcls
, ifacetype
):
129 """set up a configureable memory test of type ifacetype
132 pspec
= TestMemPspec(ldst_ifacetype
=ifacetype
,
137 cmpi
= ConfigMemoryPortInterface(pspec
)
138 dut
.submodules
.pi
= cmpi
.pi
139 if hasattr(cmpi
, 'lsmem'): # hmmm not happy about this
140 dut
.submodules
.lsmem
= cmpi
.lsmem
.lsi
141 vl
= rtlil
.convert(dut
, ports
=[]) # dut.ports())
142 with
open("test_pi_%s.il" % ifacetype
, "w") as f
:
145 run_simulation(dut
, {"sync": pi_ldst(testcls
, cmpi
.pi
.pi
)},
146 vcd_name
='test_pi_%s.vcd' % ifacetype
)
149 class TestPIMem(unittest
.TestCase
):
151 def test_pi_mem(self
):
152 tst_config_pi(self
, 'testpi')
154 def test_pi2ls(self
):
155 tst_config_pi(self
, 'testmem')
157 def test_pi2ls_bare_wb(self
):
158 tst_config_pi(self
, 'test_bare_wb')
161 if __name__
== '__main__':