src/soc/consts.py

   1 # Listed in V3.0B Book III Chap 4.2.1
   2 # MSR bit numbers
   3
   4 class MSR:
   5     SF  = (63 - 0)     # Sixty-Four bit mode
   6     HV  = (63 - 3)     # Hypervisor state
   7     S   = (63 - 41)    # Secure state
   8     EE  = (63 - 48)    # External interrupt Enable
   9     PR  = (63 - 49)    # PRoblem state
  10     FP  = (63 - 50)    # FP available
  11     ME  = (63 - 51)    # Machine Check int enable
  12     IR  = (63 - 58)    # Instruction Relocation
  13     DR  = (63 - 59)    # Data Relocation
  14     PMM = (63 - 60)    # Performance Monitor Mark
  15     RI  = (63 - 62)    # Recoverable Interrupt
  16     LE  = (63 - 63)    # Little Endian
  17
  18 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
  19
  20 # note that these correspond to trap_input_record.traptype bits 0,1,2,3
  21 # (TODO: add more?)
  22
  23 class PI:
  24     FP   = (63 - 43)    # 1 if FP exception
  25     PRIV = (63 - 45)    # 1 if privileged interrupt
  26     TRAP = (63 - 46)    # 1 if exception is "trap" type
  27     ADR  = (63 - 47)    # 0 if SRR0 = address of instruction causing exception
  28