src/soc/consts.py

   1 # sigh create little-ended versions of bitfield flags
   2 def botchify(bekls, lekls):
   3     for attr in dir(bekls):
   4         if attr[0] == '_':
   5             continue
   6         setattr(lekls, attr, 63-getattr(bekls, attr))
   7
   8
   9 # Can't think of a better place to put these functions.
  10 # Return an arbitrary subfield of a larger field.
  11 def field_slice(msb0_start, msb0_end, field_width=64):
  12     """field_slice
  13
  14     Answers with a subfield slice of the signal r ("register"),
  15     where the start and end bits use IBM "MSB 0" conventions.
  16
  17     see: https://en.wikipedia.org/wiki/Bit_numbering#MSB_0_bit_numbering
  18
  19     * assertion: msb0_start < msb0_end.
  20     * The range specified is inclusive on both ends.
  21     * field_width specifies the total number of bits (note: not bits-1)
  22     """
  23     if msb0_start >= msb0_end:
  24         raise ValueError(
  25             "start ({}) must be less than end ({})".format(start, end)
  26         )
  27     # sigh.  MSB0 (IBM numbering) is inverted.  converting to python
  28     # we *swap names* so as not to get confused by having "end, start"
  29     end = (field_width-1) - msb0_start
  30     start = (field_width-1) - msb0_end
  31
  32     return slice(start, end + 1)
  33
  34
  35 def field(r, start, end=None):
  36     """Answers with a subfield of the signal r ("register"), where
  37     the start and end bits use IBM conventions.  start < end, if
  38     end is provided.  The range specified is inclusive on both ends.
  39     """
  40     if end is None:
  41         return r[63 - start]
  42     else:
  43         return r[field_slice(start, end)]
  44
  45
  46 # Listed in V3.0B Book III Chap 4.2.1
  47 # MSR bit numbers, *bigendian* order (PowerISA format)
  48 # use this in the simulator
  49 class MSRb:
  50     SF  = 0     # Sixty-Four bit mode
  51     HV  = 3     # Hypervisor state
  52     UND = 5     # Undefined behavior state (see Bk 2, Sect. 3.2.1)
  53     TSs = 29    # Transactional State (subfield)
  54     TSe = 30    # Transactional State (subfield)
  55     TM  = 31    # Transactional Memory Available
  56     VEC = 38    # Vector Available
  57     VSX = 40    # VSX Available
  58     S   = 41    # Secure state
  59     EE  = 48    # External interrupt Enable
  60     PR  = 49    # PRoblem state
  61     FP  = 50    # FP available
  62     ME  = 51    # Machine Check int enable
  63     FE0 = 52    # Floating-Point Exception Mode 0
  64     TEs = 53    # Trace Enable (subfield)
  65     TEe = 54    # Trace Enable (subfield)
  66     FE1 = 55    # Floating-Point Exception Mode 1
  67     IR  = 58    # Instruction Relocation
  68     DR  = 59    # Data Relocation
  69     PMM = 60    # Performance Monitor Mark
  70     RI  = 62    # Recoverable Interrupt
  71     LE  = 63    # Little Endian
  72
  73 # use this inside the HDL (where everything is little-endian)
  74 class MSR:
  75     pass
  76
  77 botchify(MSRb, MSR)
  78
  79 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
  80
  81 # note that these correspond to trap_input_record.traptype bits 0,1,2,3,4
  82 # (TODO: add more?)
  83 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
  84 # to expand traptype to cope with the increased range
  85
  86 # use this in the simulator
  87 class PIb:
  88     TM_BAD_THING = 42    # 1 for a TM Bad Thing type interrupt
  89     FP           = 43    # 1 if FP exception
  90     ILLEG        = 44    # 1 if illegal instruction (not doing hypervisor)
  91     PRIV         = 45    # 1 if privileged interrupt
  92     TRAP         = 46    # 1 if exception is "trap" type
  93     ADR          = 47    # 0 if SRR0 = address of instruction causing exception
  94
  95 # and use this in the HDL
  96 class PI:
  97     pass
  98
  99 botchify(PIb, PI)
 100
 101 # see traptype (and trap main_stage.py)
 102 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
 103 # to expand traptype to cope with the increased range
 104
 105 class TT:
 106     FP = 1<<0
 107     PRIV = 1<<1
 108     TRAP = 1<<2
 109     ADDR = 1<<3
 110     ILLEG = 1<<4 # currently the max, therefore traptype must be 5 bits
 111     # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
 112     size = 5 # MUST update this to contain the full number of Trap Types