src/soc/consts.py

   1 # sigh create little-ended versions of bitfield flags
   2 def botchify(bekls, lekls):
   3     for attr in dir(bekls):
   4         if attr[0] == '_':
   5             continue
   6         setattr(lekls, attr, 63-getattr(bekls, attr))
   7
   8
   9 # Can't think of a better place to put these functions.
  10 # Return an arbitrary subfield of a larger field.
  11 def field_slice(start, end):
  12     """Answers with a subfield slice of the signal r ("register"),
  13     where the start and end bits use IBM conventions.  start < end.
  14     The range specified is inclusive on both ends.
  15     """
  16     if start >= end:
  17         raise ValueError(
  18             "start ({}) must be less than end ({})".format(start, end)
  19         )
  20     start = 63 - start
  21     end = 63 - end
  22     return slice(end, start + 1)
  23
  24
  25 def field(r, start, end=None):
  26     """Answers with a subfield of the signal r ("register"), where
  27     the start and end bits use IBM conventions.  start < end, if
  28     end is provided.  The range specified is inclusive on both ends.
  29     """
  30     if end is None:
  31         return r[63 - start]
  32     else:
  33         return r[field_slice(start, end)]
  34
  35
  36 # Listed in V3.0B Book III Chap 4.2.1
  37 # MSR bit numbers, *bigendian* order (PowerISA format)
  38 # use this in the simulator
  39 class MSRb:
  40     SF  = 0     # Sixty-Four bit mode
  41     HV  = 3     # Hypervisor state
  42     UND = 5     # Undefined behavior state (see Bk 2, Sect. 3.2.1)
  43     TSs = 29    # Transactional State (subfield)
  44     TSe = 30    # Transactional State (subfield)
  45     TM  = 31    # Transactional Memory Available
  46     VEC = 38    # Vector Available
  47     VSX = 40    # VSX Available
  48     S   = 41    # Secure state
  49     EE  = 48    # External interrupt Enable
  50     PR  = 49    # PRoblem state
  51     FP  = 50    # FP available
  52     ME  = 51    # Machine Check int enable
  53     FE0 = 52    # Floating-Point Exception Mode 0
  54     TEs = 53    # Trace Enable (subfield)
  55     TEe = 54    # Trace Enable (subfield)
  56     FE1 = 55    # Floating-Point Exception Mode 1
  57     IR  = 58    # Instruction Relocation
  58     DR  = 59    # Data Relocation
  59     PMM = 60    # Performance Monitor Mark
  60     RI  = 62    # Recoverable Interrupt
  61     LE  = 63    # Little Endian
  62
  63 # use this inside the HDL (where everything is little-endian)
  64 class MSR:
  65     pass
  66
  67 botchify(MSRb, MSR)
  68
  69 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
  70
  71 # note that these correspond to trap_input_record.traptype bits 0,1,2,3,4
  72 # (TODO: add more?)
  73 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
  74 # to expand traptype to cope with the increased range
  75
  76 # use this in the simulator
  77 class PIb:
  78     TM_BAD_THING = 42    # 1 for a TM Bad Thing type interrupt
  79     FP           = 43    # 1 if FP exception
  80     ILLEG        = 44    # 1 if illegal instruction (not doing hypervisor)
  81     PRIV         = 45    # 1 if privileged interrupt
  82     TRAP         = 46    # 1 if exception is "trap" type
  83     ADR          = 47    # 0 if SRR0 = address of instruction causing exception
  84
  85 # and use this in the HDL
  86 class PI:
  87     pass
  88
  89 botchify(PIb, PI)
  90
  91 # see traptype (and trap main_stage.py)
  92 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
  93 # to expand traptype to cope with the increased range
  94
  95 class TT:
  96     FP = 1<<0
  97     PRIV = 1<<1
  98     TRAP = 1<<2
  99     ADDR = 1<<3
 100     ILLEG = 1<<4 # currently the max, therefore traptype must be 5 bits
 101     # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
 102     size = 5 # MUST update this to contain the full number of Trap Types