1 """Decode2ToExecute1Type
3 based on Anton Blanchard microwatt decode2.vhdl
6 from nmigen
import Signal
, Record
7 from nmutil
.iocontrol
import RecordObject
8 from soc
.decoder
.power_enums
import MicrOp
, CryIn
, Function
, SPR
, LDSTMode
9 from soc
.consts
import TT
14 def __init__(self
, width
, name
):
15 name_ok
= "%s_ok" % name
16 layout
= ((name
, width
), (name_ok
, 1))
17 Record
.__init
__(self
, layout
)
18 self
.data
= getattr(self
, name
) # convenience
19 self
.ok
= getattr(self
, name_ok
) # convenience
20 self
.data
.reset_less
= True # grrr
21 self
.reset_less
= True # grrr
24 return [self
.data
, self
.ok
]
27 class Decode2ToOperand(RecordObject
):
29 def __init__(self
, name
=None):
31 RecordObject
.__init
__(self
, name
=name
)
33 # current "state" (TODO: this in its own Record)
34 self
.msr
= Signal(64, reset_less
=True)
35 self
.cia
= Signal(64, reset_less
=True)
37 # instruction, type and decoded information
38 self
.insn
= Signal(32, reset_less
=True) # original instruction
39 self
.insn_type
= Signal(MicrOp
, reset_less
=True)
40 self
.fn_unit
= Signal(Function
, reset_less
=True)
41 self
.imm_data
= Data(64, name
="imm")
42 self
.lk
= Signal(reset_less
=True)
43 self
.rc
= Data(1, "rc")
44 self
.oe
= Data(1, "oe")
45 self
.invert_in
= Signal(reset_less
=True)
46 self
.zero_a
= Signal(reset_less
=True)
47 self
.input_carry
= Signal(CryIn
, reset_less
=True)
48 self
.output_carry
= Signal(reset_less
=True)
49 self
.input_cr
= Signal(reset_less
=True) # instr. has a CR as input
50 self
.output_cr
= Signal(reset_less
=True) # instr. has a CR as output
51 self
.invert_out
= Signal(reset_less
=True)
52 self
.is_32bit
= Signal(reset_less
=True)
53 self
.is_signed
= Signal(reset_less
=True)
54 self
.data_len
= Signal(4, reset_less
=True) # bytes
55 self
.byte_reverse
= Signal(reset_less
=True)
56 self
.sign_extend
= Signal(reset_less
=True)# do we need this?
57 self
.ldst_mode
= Signal(LDSTMode
, reset_less
=True) # LD/ST mode
58 self
.traptype
= Signal(TT
.size
, reset_less
=True) # trap main_stage.py
59 self
.trapaddr
= Signal(13, reset_less
=True)
60 self
.read_cr_whole
= Data(8, "cr_rd") # CR full read mask
61 self
.write_cr_whole
= Data(8, "cr_wr") # CR full write mask
62 self
.write_cr0
= Signal(reset_less
=True)
65 class Decode2ToExecute1Type(RecordObject
):
67 def __init__(self
, name
=None, asmcode
=True):
69 RecordObject
.__init
__(self
, name
=name
)
72 self
.asmcode
= Signal(8, reset_less
=True) # only for simulator
73 self
.write_reg
= Data(5, name
="rego")
74 self
.write_ea
= Data(5, name
="ea") # for LD/ST in update mode
75 self
.read_reg1
= Data(5, name
="reg1")
76 self
.read_reg2
= Data(5, name
="reg2")
77 self
.read_reg3
= Data(5, name
="reg3")
78 self
.write_spr
= Data(SPR
, name
="spro")
79 self
.read_spr1
= Data(SPR
, name
="spr1")
80 #self.read_spr2 = Data(SPR, name="spr2") # only one needed
82 self
.xer_in
= Signal(reset_less
=True) # xer might be read
83 self
.xer_out
= Signal(reset_less
=True) # xer might be written
85 self
.read_fast1
= Data(3, name
="fast1")
86 self
.read_fast2
= Data(3, name
="fast2")
87 self
.write_fast1
= Data(3, name
="fasto1")
88 self
.write_fast2
= Data(3, name
="fasto2")
90 self
.read_cr1
= Data(3, name
="cr_in1")
91 self
.read_cr2
= Data(3, name
="cr_in2")
92 self
.read_cr3
= Data(3, name
="cr_in2")
93 self
.write_cr
= Data(3, name
="cr_out")
96 self
.do
= Decode2ToOperand(name
)