1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
16 from nmigen
.back
.pysim
import Settle
18 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
20 from soc
.decoder
.helpers
import exts
, gtu
, ltu
, undefined
21 from soc
.decoder
.isa
.mem
import Mem
22 from soc
.consts
import MSRb
# big-endian (PowerISA versions)
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift
, size
):
30 res
= SelectableInt(0, size
)
33 res
[size
-1-i
] = SelectableInt(1, 1)
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr
,shift
):
51 x
= addr
.value
>> shift
.value
52 return SelectableInt(x
,16)
71 //Accessing 2nd double word of partition table (pate1)
72 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
74 // ====================================================
75 // -----------------------------------------------
76 // | /// | PATB | /// | PATS |
77 // -----------------------------------------------
79 // PATB[4:51] holds the base address of the Partition Table,
80 // right shifted by 12 bits.
81 // This is because the address of the Partition base is
82 // 4k aligned. Hence, the lower 12bits, which are always
83 // 0 are ommitted from the PTCR.
85 // Thus, The Partition Table Base is obtained by (PATB << 12)
87 // PATS represents the partition table size right-shifted by 12 bits.
88 // The minimal size of the partition table is 4k.
89 // Thus partition table size = (1 << PATS + 12).
92 // ====================================================
93 // 0 PATE0 63 PATE1 127
94 // |----------------------|----------------------|
96 // |----------------------|----------------------|
98 // |----------------------|----------------------|
100 // |----------------------|----------------------|
104 // |----------------------|----------------------|
106 // |----------------------|----------------------|
108 // The effective LPID forms the index into the Partition Table.
110 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
111 // corresponding to that partition.
113 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
116 // -----------------------------------------------
117 // |1|RTS1|/| RPDB | RTS2 | RPDS |
118 // -----------------------------------------------
119 // 0 1 2 3 4 55 56 58 59 63
121 // HR[0] : For Radix Page table, first bit should be 1.
122 // RTS1[1:2] : Gives one fragment of the Radix treesize
123 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
124 // RTS = (RTS1 << 3 + RTS2) + 31.
126 // RPDB[4:55] = Root Page Directory Base.
127 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
128 // Thus, Root page directory size = 1 << (RPDS + 3).
132 // -----------------------------------------------
133 // |///| PRTB | // | PRTS |
134 // -----------------------------------------------
135 // 0 3 4 51 52 58 59 63
137 // PRTB[4:51] = Process Table Base. This is aligned to size.
138 // PRTS[59: 63] = Process Table Size right shifted by 12.
139 // Minimal size of the process table is 4k.
140 // Process Table Size = (1 << PRTS + 12).
143 // Computing the size aligned Process Table Base:
144 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
145 // Thus, the lower 12+PRTS bits of table_base will
149 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
152 // ==========================
153 // 0 PRTE0 63 PRTE1 127
154 // |----------------------|----------------------|
156 // |----------------------|----------------------|
158 // |----------------------|----------------------|
160 // |----------------------|----------------------|
164 // |----------------------|----------------------|
166 // |----------------------|----------------------|
168 // The effective Process id (PID) forms the index into the Process Table.
170 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
171 // corresponding to that process
173 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
176 // -----------------------------------------------
177 // |/|RTS1|/| RPDB | RTS2 | RPDS |
178 // -----------------------------------------------
179 // 0 1 2 3 4 55 56 58 59 63
181 // RTS1[1:2] : Gives one fragment of the Radix treesize
182 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
183 // RTS = (RTS1 << 3 + RTS2) << 31,
184 // since minimal Radix Tree size is 4G.
186 // RPDB = Root Page Directory Base.
187 // RPDS = Root Page Directory Size right shifted by 3.
188 // Thus, Root page directory size = RPDS << 3.
192 // -----------------------------------------------
194 // -----------------------------------------------
196 // All bits are reserved.
204 0x10000: # PARTITION_TABLE_2 (not implemented yet)
205 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
208 0x30000: # RADIX_ROOT_PTE
209 # V = 1 L = 0 NLB = 0x400 NLS = 9
211 ######## 0x4000000 #### wrong address calculated by _get_pgtable_addr
212 0x40000: # RADIX_SECOND_LEVEL
213 # V = 1 L = 1 SW = 0 RPN = 0
214 # R = 1 C = 1 ATT = 0 EAA 0x7
217 0x1000000: # PROCESS_TABLE_3
218 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
224 # see qemu/target/ppc/mmu-radix64.c for reference
226 def __init__(self
, mem
, caller
):
229 if caller
is not None:
230 self
.dsisr
= self
.caller
.spr
["DSISR"]
231 self
.dar
= self
.caller
.spr
["DAR"]
232 self
.pidr
= self
.caller
.spr
["PIDR"]
233 self
.prtbl
= self
.caller
.spr
["PRTBL"]
234 self
.msr
= self
.caller
.msr
236 # cached page table stuff
238 self
.pt0_valid
= False
240 self
.pt3_valid
= False
242 def __call__(self
, addr
, sz
):
243 val
= self
.ld(addr
.value
, sz
, swap
=False)
244 print("RADIX memread", addr
, sz
, val
)
245 return SelectableInt(val
, sz
*8)
247 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False,
249 print("RADIX: ld from addr 0x%x width %d" % (address
, width
))
251 priv
= ~
(self
.msr(MSR_PR
).value
) # problem-state ==> privileged
256 addr
= SelectableInt(address
, 64)
257 (shift
, mbits
, pgbase
) = self
._decode
_prte
(addr
)
258 #shift = SelectableInt(0, 32)
260 pte
= self
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
, priv
)
261 # use pte to caclculate phys address
262 return self
.mem
.ld(address
, width
, swap
, check_in_mem
)
264 # XXX set SPRs on error
267 def st(self
, address
, v
, width
=8, swap
=True):
268 print("RADIX: st to addr 0x%x width %d data %x" % (address
, width
, v
))
270 priv
= ~
(self
.msr(MSR_PR
).value
) # problem-state ==> privileged
272 addr
= SelectableInt(address
, 64)
273 (shift
, mbits
, pgbase
) = self
._decode
_prte
(addr
)
274 pte
= self
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
, priv
)
276 # use pte to caclculate phys address (addr)
277 return self
.mem
.st(addr
.value
, v
, width
, swap
)
279 # XXX set SPRs on error
281 def memassign(self
, addr
, sz
, val
):
282 print("memassign", addr
, sz
, val
)
283 self
.st(addr
.value
, val
.value
, sz
, swap
=False)
285 def _next_level(self
, addr
, entry_width
, swap
, check_in_mem
):
286 # implement read access to mmu mem here
289 if addr
.value
in testmem
:
290 value
= testmem
[addr
.value
]
294 ##value = self.mem.ld(addr.value, entry_width, swap, check_in_mem)
295 print("addr", hex(addr
.value
))
296 data
= SelectableInt(value
, 64) # convert to SelectableInt
297 print("value", hex(value
))
301 def _walk_tree(self
, addr
, pgbase
, mode
, mbits
, shift
, priv
=1):
305 // vaddr |-----------------------------------------------------|
307 // |-----------|-----------------------------------------|
308 // | 0000000 | usefulBits = X bits (typically 52) |
309 // |-----------|-----------------------------------------|
310 // | |<--Cursize---->| |
314 // |-----------------------------------------------------|
317 // PDE |---------------------------| |
318 // |V|L|//| NLB |///|NLS| |
319 // |---------------------------| |
320 // PDE = Page Directory Entry |
321 // [0] = V = Valid Bit |
322 // [1] = L = Leaf bit. If 0, then |
323 // [4:55] = NLB = Next Level Base |
324 // right shifted by 8 |
325 // [59:63] = NLS = Next Level Size |
328 // | |--------------------------|
329 // | | usfulBits = X-Cursize |
330 // | |--------------------------|
331 // |---------------------><--NLS-->| |
335 // |--------------------------|
337 // If the next PDE obtained by |
338 // (NLB << 8 + 8 * index) is a |
339 // nonleaf, then repeat the above. |
341 // If the next PDE is a leaf, |
342 // then Leaf PDE structure is as |
347 // |------------------------------| |----------------|
348 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
349 // |------------------------------| |----------------|
350 // [0] = V = Valid Bit |
351 // [1] = L = Leaf Bit = 1 if leaf |
353 // [2] = Sw = Sw bit 0. |
354 // [7:51] = RPN = Real Page Number, V
355 // real_page = RPN << 12 -------------> Logical OR
356 // [52:54] = Sw Bits 1:3 |
357 // [55] = R = Reference |
358 // [56] = C = Change V
359 // [58:59] = Att = Physical Address
360 // 0b00 = Normal Memory
362 // 0b10 = Non Idenmpotent
363 // 0b11 = Tolerant I/O
364 // [60:63] = Encoded Access
370 pidr
= self
.caller
.spr
["PIDR"]
371 prtbl
= self
.caller
.spr
["PRTBL"]
375 print("last 8 bits ----------")
378 prtbl
= SelectableInt(0x1000000,64) #FIXME do not hardcode
380 # get address of root entry
381 shift
= selectconcat(SelectableInt(0,1),prtbl
[58:63]) # TODO verify
382 addr_next
= self
._get
_prtable
_addr
(shift
, prtbl
, addr
, pidr
)
383 print("starting with addr_next",addr_next
)
385 assert(addr_next
.bits
==64)
386 assert(addr_next
.value
==0x1000000) #TODO
388 addr_next
= SelectableInt(0x30000,64) # radix root for testing
390 # walk tree starts on prtbl
392 print("nextlevel----------------------------")
398 data
= self
._next
_level
(addr_next
, entry_width
, swap
, check_in_mem
)
399 valid
= rpte_valid(data
)
400 leaf
= rpte_leaf(data
)
402 print(" valid, leaf", valid
, leaf
)
404 return "invalid" # TODO: return error
406 ok
= self
._check
_perms
(data
, priv
, mode
)
407 if ok
== True: # data was ok, found phys address, return it?
409 return ok
# return the error code
411 newlookup
= self
._new
_lookup
(data
, mbits
, shift
)
412 if newlookup
== 'badtree':
414 shift
, mask
, pgbase
= newlookup
415 print (" next level", shift
, mask
, pgbase
)
416 shift
= SelectableInt(shift
.value
,16) #THIS is wrong !!!
417 print("calling _get_pgtable_addr")
418 print(mask
) #SelectableInt(value=0x9, bits=4)
419 print(pgbase
) #SelectableInt(value=0x40000, bits=56)
420 print(shift
) #SelectableInt(value=0x4, bits=16) #FIXME
421 pgbase
= SelectableInt(pgbase
.value
,64)
422 addrsh
= addrshift(addr
,shift
)
423 addr_next
= self
._get
_pgtable
_addr
(mask
, pgbase
, addrsh
)
424 print("addr_next",addr_next
)
425 print("addrsh",addrsh
)
427 def _new_lookup(self
, data
, mbits
, shift
):
429 mbits := unsigned('0' & data(4 downto 0));
430 if mbits < 5 or mbits > 16 or mbits > r.shift then
431 v.state := RADIX_FINISH;
432 v.badtree := '1'; -- throw error
434 v.shift := v.shift - mbits;
435 v.mask_size := mbits(4 downto 0);
436 v.pgbase := data(55 downto 8) & x"00"; NLB?
437 v.state := RADIX_LOOKUP; --> next level
441 print("mbits=", mbits
)
442 if mbits
< 5 or mbits
> 16: #fixme compare with r.shift
445 # reduce shift (has to be done at same bitwidth)
446 shift
= shift
- selectconcat(SelectableInt(0, 1), mbits
)
447 mask_size
= mbits
[1:5] # get 4 LSBs
448 pgbase
= selectconcat(data
[8:56], SelectableInt(0, 8)) # shift up 8
449 return shift
, mask_size
, pgbase
451 def _decode_prte(self
, data
):
453 -----------------------------------------------
454 |/|RTS1|/| RPDB | RTS2 | RPDS |
455 -----------------------------------------------
456 0 1 2 3 4 55 56 58 59 63
458 # note that SelectableInt does big-endian! so the indices
459 # below *directly* match the spec, unlike microwatt which
460 # has to turn them around (to LE)
461 zero
= SelectableInt(0, 1)
462 rts
= selectconcat(zero
,
466 masksize
= data
[59:64] # RPDS
467 mbits
= selectconcat(zero
, masksize
)
468 pgbase
= selectconcat(data
[8:56], # part of RPDB
469 SelectableInt(0, 16),)
471 return (rts
, mbits
, pgbase
)
473 def _segment_check(self
, addr
, mbits
, shift
):
474 """checks segment valid
475 mbits := '0' & r.mask_size;
476 v.shift := r.shift + (31 - 12) - mbits;
477 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
478 if r.addr(63) /= r.addr(62) or nonzero = '1' then
479 v.state := RADIX_FINISH;
481 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
482 v.state := RADIX_FINISH;
485 v.state := RADIX_LOOKUP;
487 # note that SelectableInt does big-endian! so the indices
488 # below *directly* match the spec, unlike microwatt which
489 # has to turn them around (to LE)
490 mask
= genmask(shift
, 44)
491 nonzero
= addr
[1:32] & mask
[13:44] # mask 31 LSBs (BE numbered 13:44)
492 print ("RADIX _segment_check nonzero", bin(nonzero
.value
))
493 print ("RADIX _segment_check addr[0-1]", addr
[0].value
, addr
[1].value
)
494 if addr
[0] != addr
[1] or nonzero
!= 0:
496 limit
= shift
+ (31 - 12)
497 if mbits
< 5 or mbits
> 16 or mbits
> limit
:
499 new_shift
= shift
+ (31 - 12) - mbits
502 def _check_perms(self
, data
, priv
, mode
):
503 """check page permissions
505 // |------------------------------| |----------------|
506 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
507 // |------------------------------| |----------------|
508 // [0] = V = Valid Bit |
509 // [1] = L = Leaf Bit = 1 if leaf |
511 // [2] = Sw = Sw bit 0. |
512 // [7:51] = RPN = Real Page Number, V
513 // real_page = RPN << 12 -------------> Logical OR
514 // [52:54] = Sw Bits 1:3 |
515 // [55] = R = Reference |
516 // [56] = C = Change V
517 // [58:59] = Att = Physical Address
518 // 0b00 = Normal Memory
520 // 0b10 = Non Idenmpotent
521 // 0b11 = Tolerant I/O
522 // [60:63] = Encoded Access
526 -- check permissions and RC bits
528 if r.priv = '1' or data(3) = '0' then
529 if r.iside = '0' then
530 perm_ok := data(1) or (data(2) and not r.store);
532 -- no IAMR, so no KUEP support for now
533 -- deny execute permission if cache inhibited
534 perm_ok := data(0) and not data(5);
537 rc_ok := data(8) and (data(7) or not r.store);
538 if perm_ok = '1' and rc_ok = '1' then
539 v.state := RADIX_LOAD_TLB;
541 v.state := RADIX_FINISH;
542 v.perm_err := not perm_ok;
543 -- permission error takes precedence over RC error
544 v.rc_error := perm_ok;
547 # decode mode into something that matches microwatt equivalent code
548 instr_fetch
, store
= 0, 0
551 if mode
== 'EXECUTE':
554 # check permissions and RC bits
556 if priv
== 1 or data
[60] == 0:
558 perm_ok
= data
[62] |
(data
[61] & (store
== 0))
559 # no IAMR, so no KUEP support for now
560 # deny execute permission if cache inhibited
561 perm_ok
= data
[63] & ~data
[58]
562 rc_ok
= data
[55] & (data
[56] |
(store
== 0))
563 if perm_ok
== 1 and rc_ok
== 1:
566 return "perm_err" if perm_ok
== 0 else "rc_err"
568 def _get_prtable_addr(self
, shift
, prtbl
, addr
, pid
):
570 if r.addr(63) = '1' then
571 effpid := x"00000000";
575 x"00" & r.prtbl(55 downto 36) &
576 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
577 (effpid(31 downto 8) and finalmask(23 downto 0))) &
578 effpid(7 downto 0) & "0000";
580 print ("_get_prtable_addr_", shift
, prtbl
, addr
, pid
)
581 finalmask
= genmask(shift
, 44)
582 finalmask24
= finalmask
[20:44]
583 if addr
[0].value
== 1:
584 effpid
= SelectableInt(0, 32)
586 effpid
= pid
#self.pid # TODO, check on this
587 zero8
= SelectableInt(0, 8)
588 zero4
= SelectableInt(0, 4)
589 res
= selectconcat(zero8
,
591 (prtbl
[28:52] & ~finalmask24
) |
#
592 (effpid
[0:24] & finalmask24
), #
598 def _get_pgtable_addr(self
, mask_size
, pgbase
, addrsh
):
600 x"00" & r.pgbase(55 downto 19) &
601 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
604 mask16
= genmask(mask_size
+5, 16)
605 zero8
= SelectableInt(0, 8)
606 zero3
= SelectableInt(0, 3)
607 res
= selectconcat(zero8
,
609 (pgbase
[45:61] & ~mask16
) |
#
615 def _get_pte(self
, shift
, addr
, pde
):
618 ((r.pde(55 downto 12) and not finalmask) or
619 (r.addr(55 downto 12) and finalmask))
620 & r.pde(11 downto 0);
622 finalmask
= genmask(shift
, 44)
623 zero8
= SelectableInt(0, 8)
624 res
= selectconcat(zero8
,
625 (pde
[8:52] & ~finalmask
) |
#
626 (addr
[8:52] & finalmask
), #
637 translated done 1 err 0 badtree 0 addr 40000 pte 0
640 class TestRadixMMU(unittest
.TestCase
):
642 def test_genmask(self
):
643 shift
= SelectableInt(5, 6)
644 mask
= genmask(shift
, 43)
645 print (" mask", bin(mask
.value
))
647 self
.assertEqual(sum([1, 2, 3]), 6, "Should be 6")
649 def test_get_pgtable_addr(self
):
653 dut
= RADIX(mem
, caller
)
656 pgbase
= SelectableInt(0,64)
657 addrsh
= SelectableInt(0,16)
658 ret
= dut
._get
_pgtable
_addr
(mask_size
, pgbase
, addrsh
)
662 def test_walk_tree(self
):
663 # set up dummy minimal ISACaller
664 spr
= {'DSISR': SelectableInt(0, 64),
665 'DAR': SelectableInt(0, 64),
666 'PIDR': SelectableInt(0, 64),
667 'PRTBL': SelectableInt(0, 64)
669 # set problem state == 0 (other unit tests, set to 1)
670 msr
= SelectableInt(0, 64)
672 class ISACaller
: pass
677 shift
= SelectableInt(5, 6)
678 mask
= genmask(shift
, 43)
679 print (" mask", bin(mask
.value
))
681 mem
= Mem(row_bytes
=8)
682 mem
= RADIX(mem
, caller
)
683 # -----------------------------------------------
684 # |/|RTS1|/| RPDB | RTS2 | RPDS |
685 # -----------------------------------------------
686 # |0|1 2|3|4 55|56 58|59 63|
687 data
= SelectableInt(0, 64)
690 data
[59:64] = 0b01101 # mask
692 (rts
, mbits
, pgbase
) = mem
._decode
_prte
(data
)
693 print (" rts", bin(rts
.value
), rts
.bits
)
694 print (" mbits", bin(mbits
.value
), mbits
.bits
)
695 print (" pgbase", hex(pgbase
.value
), pgbase
.bits
)
696 addr
= SelectableInt(0x1000, 64)
697 check
= mem
._segment
_check
(addr
, mbits
, shift
)
698 print (" segment check", check
)
700 print("walking tree")
701 addr
= SelectableInt(testaddr
,64)
706 result
= mem
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
)
707 print(" walking tree result", result
)
710 if __name__
== '__main__':