projects / soc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
create iterative mmu lookup loop
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22
23 import math
24 import sys
25
26 # very quick, TODO move to SelectableInt utils later
27 def genmask(shift, size):
28 res = SelectableInt(0, size)
29 for i in range(size):
30 if i < shift:
31 res[size-1-i] = SelectableInt(1, 1)
32 return res
33
34 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
35 # MSB is indexed **LOWEST** (sigh)
36 # from gem5 radixwalk.hh
37 # Bitfield<63> valid; 64 - (63 + 1) = 0
38 # Bitfield<62> leaf; 64 - (62 + 1) = 1
39
40 def rpte_valid(r):
41 return bool(r[0])
42
43 def rpte_leaf(r):
44 return bool(r[1])
45
46 def NLB(x):
47 """
48 Next Level Base
49 right shifted by 8
50 """
51 return x[4:55]
52
53 def NLS(x):
54 """
55 Next Level Size
56 NLS >= 5
57 """
58 return x[59:63]
59
60 """
61 Get Root Page
62
63 //Accessing 2nd double word of partition table (pate1)
64 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
65 // PTCR Layout
66 // ====================================================
67 // -----------------------------------------------
68 // | /// | PATB | /// | PATS |
69 // -----------------------------------------------
70 // 0 4 51 52 58 59 63
71 // PATB[4:51] holds the base address of the Partition Table,
72 // right shifted by 12 bits.
73 // This is because the address of the Partition base is
74 // 4k aligned. Hence, the lower 12bits, which are always
75 // 0 are ommitted from the PTCR.
76 //
77 // Thus, The Partition Table Base is obtained by (PATB << 12)
78 //
79 // PATS represents the partition table size right-shifted by 12 bits.
80 // The minimal size of the partition table is 4k.
81 // Thus partition table size = (1 << PATS + 12).
82 //
83 // Partition Table
84 // ====================================================
85 // 0 PATE0 63 PATE1 127
86 // |----------------------|----------------------|
87 // | | |
88 // |----------------------|----------------------|
89 // | | |
90 // |----------------------|----------------------|
91 // | | | <-- effLPID
92 // |----------------------|----------------------|
93 // .
94 // .
95 // .
96 // |----------------------|----------------------|
97 // | | |
98 // |----------------------|----------------------|
99 //
100 // The effective LPID forms the index into the Partition Table.
101 //
102 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
103 // corresponding to that partition.
104 //
105 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
106 //
107 // PATE0 Layout
108 // -----------------------------------------------
109 // |1|RTS1|/| RPDB | RTS2 | RPDS |
110 // -----------------------------------------------
111 // 0 1 2 3 4 55 56 58 59 63
112 //
113 // HR[0] : For Radix Page table, first bit should be 1.
114 // RTS1[1:2] : Gives one fragment of the Radix treesize
115 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
116 // RTS = (RTS1 << 3 + RTS2) + 31.
117 //
118 // RPDB[4:55] = Root Page Directory Base.
119 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
120 // Thus, Root page directory size = 1 << (RPDS + 3).
121 // Note: RPDS >= 5.
122 //
123 // PATE1 Layout
124 // -----------------------------------------------
125 // |///| PRTB | // | PRTS |
126 // -----------------------------------------------
127 // 0 3 4 51 52 58 59 63
128 //
129 // PRTB[4:51] = Process Table Base. This is aligned to size.
130 // PRTS[59: 63] = Process Table Size right shifted by 12.
131 // Minimal size of the process table is 4k.
132 // Process Table Size = (1 << PRTS + 12).
133 // Note: PRTS <= 24.
134 //
135 // Computing the size aligned Process Table Base:
136 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
137 // Thus, the lower 12+PRTS bits of table_base will
138 // be zero.
139
140
141 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
142 //
143 // Process Table
144 // ==========================
145 // 0 PRTE0 63 PRTE1 127
146 // |----------------------|----------------------|
147 // | | |
148 // |----------------------|----------------------|
149 // | | |
150 // |----------------------|----------------------|
151 // | | | <-- effPID
152 // |----------------------|----------------------|
153 // .
154 // .
155 // .
156 // |----------------------|----------------------|
157 // | | |
158 // |----------------------|----------------------|
159 //
160 // The effective Process id (PID) forms the index into the Process Table.
161 //
162 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
163 // corresponding to that process
164 //
165 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
166 //
167 // PRTE0 Layout
168 // -----------------------------------------------
169 // |/|RTS1|/| RPDB | RTS2 | RPDS |
170 // -----------------------------------------------
171 // 0 1 2 3 4 55 56 58 59 63
172 //
173 // RTS1[1:2] : Gives one fragment of the Radix treesize
174 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
175 // RTS = (RTS1 << 3 + RTS2) << 31,
176 // since minimal Radix Tree size is 4G.
177 //
178 // RPDB = Root Page Directory Base.
179 // RPDS = Root Page Directory Size right shifted by 3.
180 // Thus, Root page directory size = RPDS << 3.
181 // Note: RPDS >= 5.
182 //
183 // PRTE1 Layout
184 // -----------------------------------------------
185 // | /// |
186 // -----------------------------------------------
187 // 0 63
188 // All bits are reserved.
189
190
191 """
192
193 # see qemu/target/ppc/mmu-radix64.c for reference
194 class RADIX:
195 def __init__(self, mem, caller):
196 self.mem = mem
197 self.caller = caller
198 #TODO move to lookup
199 self.dsisr = self.caller.spr["DSISR"]
200 self.dar = self.caller.spr["DAR"]
201 self.pidr = self.caller.spr["PIDR"]
202 self.prtbl = self.caller.spr["PRTBL"]
203
204 # cached page table stuff
205 self.pgtbl0 = 0
206 self.pt0_valid = False
207 self.pgtbl3 = 0
208 self.pt3_valid = False
209
210 def __call__(self, addr, sz):
211 val = self.ld(addr.value, sz, swap=False)
212 print("RADIX memread", addr, sz, val)
213 return SelectableInt(val, sz*8)
214
215 def ld(self, address, width=8, swap=True, check_in_mem=False,
216 instr_fetch=False):
217 print("RADIX: ld from addr 0x%x width %d" % (address, width))
218
219 priv = 1 # XXX TODO: read MSR PR bit here priv = not ctrl.msr(MSR_PR);
220 if instr_fetch:
221 mode = 'EXECUTE'
222 else:
223 mode = 'LOAD'
224 addr = SelectableInt(address, 64)
225 (shift, mbits, pgbase) = self._decode_prte(addr)
226 #shift = SelectableInt(0, 32)
227
228 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
229 # use pte to caclculate phys address
230 return self.mem.ld(address, width, swap, check_in_mem)
231
232 # XXX set SPRs on error
233
234 # TODO implement
235 def st(self, address, v, width=8, swap=True):
236 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
237
238 priv = 1 # XXX TODO: read MSR PR bit here priv = not ctrl.msr(MSR_PR);
239 mode = 'STORE'
240 addr = SelectableInt(address, 64)
241 (shift, mbits, pgbase) = self._decode_prte(addr)
242 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
243
244 # use pte to caclculate phys address (addr)
245 return self.mem.st(addr.value, v, width, swap)
246
247 # XXX set SPRs on error
248
249 def memassign(self, addr, sz, val):
250 print("memassign", addr, sz, val)
251 self.st(addr.value, val.value, sz, swap=False)
252
253 def _next_level(self, addr, entry_width, swap, check_in_mem):
254 # implement read access to mmu mem here
255 value = self.mem.ld(addr.value, entry_width, swap, check_in_mem)
256 print("addr",addr.value)
257 data = SelectableInt(value, 64) # convert to SelectableInt
258 print("value",value)
259 # index += 1
260 return data;
261
262 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
263 """walk tree
264
265 // vaddr 64 Bit
266 // vaddr |-----------------------------------------------------|
267 // | Unused | Used |
268 // |-----------|-----------------------------------------|
269 // | 0000000 | usefulBits = X bits (typically 52) |
270 // |-----------|-----------------------------------------|
271 // | |<--Cursize---->| |
272 // | | Index | |
273 // | | into Page | |
274 // | | Directory | |
275 // |-----------------------------------------------------|
276 // | |
277 // V |
278 // PDE |---------------------------| |
279 // |V|L|//| NLB |///|NLS| |
280 // |---------------------------| |
281 // PDE = Page Directory Entry |
282 // [0] = V = Valid Bit |
283 // [1] = L = Leaf bit. If 0, then |
284 // [4:55] = NLB = Next Level Base |
285 // right shifted by 8 |
286 // [59:63] = NLS = Next Level Size |
287 // | NLS >= 5 |
288 // | V
289 // | |--------------------------|
290 // | | usfulBits = X-Cursize |
291 // | |--------------------------|
292 // |---------------------><--NLS-->| |
293 // | Index | |
294 // | into | |
295 // | PDE | |
296 // |--------------------------|
297 // |
298 // If the next PDE obtained by |
299 // (NLB << 8 + 8 * index) is a |
300 // nonleaf, then repeat the above. |
301 // |
302 // If the next PDE is a leaf, |
303 // then Leaf PDE structure is as |
304 // follows |
305 // |
306 // |
307 // Leaf PDE |
308 // |------------------------------| |----------------|
309 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
310 // |------------------------------| |----------------|
311 // [0] = V = Valid Bit |
312 // [1] = L = Leaf Bit = 1 if leaf |
313 // PDE |
314 // [2] = Sw = Sw bit 0. |
315 // [7:51] = RPN = Real Page Number, V
316 // real_page = RPN << 12 -------------> Logical OR
317 // [52:54] = Sw Bits 1:3 |
318 // [55] = R = Reference |
319 // [56] = C = Change V
320 // [58:59] = Att = Physical Address
321 // 0b00 = Normal Memory
322 // 0b01 = SAO
323 // 0b10 = Non Idenmpotent
324 // 0b11 = Tolerant I/O
325 // [60:63] = Encoded Access
326 // Authority
327 //
328 """
329 # get sprs
330 print("_walk_tree")
331 pidr = self.caller.spr["PIDR"]
332 prtbl = self.caller.spr["PRTBL"]
333 print(pidr)
334 print(prtbl)
335 p = addr[55:63]
336 print("last 8 bits ----------")
337 print
338
339 # get address of root entry
340 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
341
342 #test_input = [
343 # SelectableInt(0x8000000000000007, 64), #valid
344 # SelectableInt(0xc000000000000000, 64) #exit
345 #]
346 #index = 0
347
348 # walk tree starts on prtbl
349 while True:
350 print("nextlevel----------------------------")
351 # read an entry
352 swap = False
353 check_in_mem = False
354 entry_width = 8
355
356 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
357 valid = rpte_valid(data)
358 leaf = rpte_leaf(data)
359
360 print(" valid, leaf", valid, leaf)
361 if not valid:
362 return None # TODO: return error
363 if leaf:
364 ok = self._check_perms(data, priv, mode)
365 # TODO: check permissions
366 # then calculate phys address
367 return None # TODO return something
368 # physical address if no error ?
369 else:
370 data = l # TODO put actual data here
371 newlookup = self._new_lookup(data, mbits, shift)
372 if newlookup == 'badtree':
373 return None
374 shift, mask, pgbase = newlookup
375 print (" next level", shift, mask, pgbase)
376 next_addr = self._get_pgtable_addr(mask, pgbase, shift)
377
378 def _new_lookup(self, data, mbits, shift):
379 """
380 mbits := unsigned('0' & data(4 downto 0));
381 if mbits < 5 or mbits > 16 or mbits > r.shift then
382 v.state := RADIX_FINISH;
383 v.badtree := '1'; -- throw error
384 else
385 v.shift := v.shift - mbits;
386 v.mask_size := mbits(4 downto 0);
387 v.pgbase := data(55 downto 8) & x"00"; NLB?
388 v.state := RADIX_LOOKUP; --> next level
389 end if;
390 """
391 mbits = data[59:64]
392 print("mbits=", mbits)
393 if mbits < 5 or mbits > 16: #fixme compare with r.shift
394 print("badtree")
395 return "badtree"
396 # reduce shift (has to be done at same bitwidth)
397 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
398 mask_size = mbits[1:5] # get 4 LSBs
399 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
400 return shift, mask_size, pgbase
401
402 def _decode_prte(self, data):
403 """PRTE0 Layout
404 -----------------------------------------------
405 |/|RTS1|/| RPDB | RTS2 | RPDS |
406 -----------------------------------------------
407 0 1 2 3 4 55 56 58 59 63
408 """
409 # note that SelectableInt does big-endian! so the indices
410 # below *directly* match the spec, unlike microwatt which
411 # has to turn them around (to LE)
412 zero = SelectableInt(0, 1)
413 rts = selectconcat(zero,
414 data[56:59], # RTS2
415 data[1:3], # RTS1
416 )
417 masksize = data[59:64] # RPDS
418 mbits = selectconcat(zero, masksize)
419 pgbase = selectconcat(data[8:56], # part of RPDB
420 SelectableInt(0, 16),)
421
422 return (rts, mbits, pgbase)
423
424 def _segment_check(self, addr, mbits, shift):
425 """checks segment valid
426 mbits := '0' & r.mask_size;
427 v.shift := r.shift + (31 - 12) - mbits;
428 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
429 if r.addr(63) /= r.addr(62) or nonzero = '1' then
430 v.state := RADIX_FINISH;
431 v.segerror := '1';
432 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
433 v.state := RADIX_FINISH;
434 v.badtree := '1';
435 else
436 v.state := RADIX_LOOKUP;
437 """
438 # note that SelectableInt does big-endian! so the indices
439 # below *directly* match the spec, unlike microwatt which
440 # has to turn them around (to LE)
441 mask = genmask(shift, 44)
442 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
443 print ("RADIX _segment_check nonzero", bin(nonzero.value))
444 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
445 if addr[0] != addr[1] or nonzero == 1:
446 return "segerror"
447 limit = shift + (31 - 12)
448 if mbits < 5 or mbits > 16 or mbits > limit:
449 return "badtree"
450 new_shift = shift + (31 - 12) - mbits
451 return new_shift
452
453 def _check_perms(self, data, priv, mode):
454 """check page permissions
455 // Leaf PDE |
456 // |------------------------------| |----------------|
457 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
458 // |------------------------------| |----------------|
459 // [0] = V = Valid Bit |
460 // [1] = L = Leaf Bit = 1 if leaf |
461 // PDE |
462 // [2] = Sw = Sw bit 0. |
463 // [7:51] = RPN = Real Page Number, V
464 // real_page = RPN << 12 -------------> Logical OR
465 // [52:54] = Sw Bits 1:3 |
466 // [55] = R = Reference |
467 // [56] = C = Change V
468 // [58:59] = Att = Physical Address
469 // 0b00 = Normal Memory
470 // 0b01 = SAO
471 // 0b10 = Non Idenmpotent
472 // 0b11 = Tolerant I/O
473 // [60:63] = Encoded Access
474 // Authority
475 //
476 -- test leaf bit
477 -- check permissions and RC bits
478 perm_ok := '0';
479 if r.priv = '1' or data(3) = '0' then
480 if r.iside = '0' then
481 perm_ok := data(1) or (data(2) and not r.store);
482 else
483 -- no IAMR, so no KUEP support for now
484 -- deny execute permission if cache inhibited
485 perm_ok := data(0) and not data(5);
486 end if;
487 end if;
488 rc_ok := data(8) and (data(7) or not r.store);
489 if perm_ok = '1' and rc_ok = '1' then
490 v.state := RADIX_LOAD_TLB;
491 else
492 v.state := RADIX_FINISH;
493 v.perm_err := not perm_ok;
494 -- permission error takes precedence over RC error
495 v.rc_error := perm_ok;
496 end if;
497 """
498 # decode mode into something that matches microwatt equivalent code
499 instr_fetch, store = 0, 0
500 if mode == 'STORE':
501 store = 1
502 if mode == 'EXECUTE':
503 inst_fetch = 1
504
505 # check permissions and RC bits
506 perm_ok = 0
507 if priv == 1 or data[60] == 0:
508 if instr_fetch == 0:
509 perm_ok = data[62] | (data[61] & (store == 0))
510 # no IAMR, so no KUEP support for now
511 # deny execute permission if cache inhibited
512 perm_ok = data[63] & ~data[58]
513 rc_ok = data[55] & (data[56] | (store == 0))
514 if perm_ok == 1 and rc_ok == 1:
515 return True
516
517 return "perm_err" if perm_ok == 0 else "rc_err"
518
519 def _get_prtable_addr(self, shift, prtbl, addr, pid):
520 """
521 if r.addr(63) = '1' then
522 effpid := x"00000000";
523 else
524 effpid := r.pid;
525 end if;
526 x"00" & r.prtbl(55 downto 36) &
527 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
528 (effpid(31 downto 8) and finalmask(23 downto 0))) &
529 effpid(7 downto 0) & "0000";
530 """
531 print ("_get_prtable_addr_", shift, prtbl, addr, pid)
532 finalmask = genmask(shift, 44)
533 finalmask24 = finalmask[20:44]
534 if addr[0].value == 1:
535 effpid = SelectableInt(0, 32)
536 else:
537 effpid = pid #self.pid # TODO, check on this
538 zero16 = SelectableInt(0, 16)
539 zero4 = SelectableInt(0, 4)
540 res = selectconcat(zero16,
541 prtbl[8:28], #
542 (prtbl[28:52] & ~finalmask24) | #
543 (effpid[0:24] & finalmask24), #
544 effpid[24:32],
545 zero4
546 )
547 return res
548
549 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
550 """
551 x"00" & r.pgbase(55 downto 19) &
552 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
553 "000";
554 """
555 mask16 = genmask(mask_size+5, 16)
556 zero8 = SelectableInt(0, 8)
557 zero3 = SelectableInt(0, 3)
558 res = selectconcat(zero8,
559 pgbase[8:45], #
560 (prtbl[45:61] & ~mask16) | #
561 (addrsh & mask16), #
562 zero3
563 )
564 return res
565
566 def _get_pte(self, shift, addr, pde):
567 """
568 x"00" &
569 ((r.pde(55 downto 12) and not finalmask) or
570 (r.addr(55 downto 12) and finalmask))
571 & r.pde(11 downto 0);
572 """
573 finalmask = genmask(shift, 44)
574 zero8 = SelectableInt(0, 8)
575 res = selectconcat(zero8,
576 (pde[8:52] & ~finalmask) | #
577 (addr[8:52] & finalmask), #
578 pde[52:64],
579 )
580 return res
581
582
583 # very quick test of maskgen function (TODO, move to util later)
584 if __name__ == '__main__':
585 # set up dummy minimal ISACaller
586 spr = {'DSISR': SelectableInt(0, 64),
587 'DAR': SelectableInt(0, 64),
588 'PIDR': SelectableInt(0, 64),
589 'PRTBL': SelectableInt(0, 64)
590 }
591 class ISACaller: pass
592 caller = ISACaller()
593 caller.spr = spr
594
595 shift = SelectableInt(5, 6)
596 mask = genmask(shift, 43)
597 print (" mask", bin(mask.value))
598
599 mem = Mem(row_bytes=8)
600 mem = RADIX(mem, caller)
601 # -----------------------------------------------
602 # |/|RTS1|/| RPDB | RTS2 | RPDS |
603 # -----------------------------------------------
604 # |0|1 2|3|4 55|56 58|59 63|
605 data = SelectableInt(0, 64)
606 data[1:3] = 0b01
607 data[56:59] = 0b11
608 data[59:64] = 0b01101 # mask
609 data[55] = 1
610 (rts, mbits, pgbase) = mem._decode_prte(data)
611 print (" rts", bin(rts.value), rts.bits)
612 print (" mbits", bin(mbits.value), mbits.bits)
613 print (" pgbase", hex(pgbase.value), pgbase.bits)
614 addr = SelectableInt(0x1000, 64)
615 check = mem._segment_check(addr, mbits, shift)
616 print (" segment check", check)
617
618 print("walking tree")
619 # addr = unchanged
620 # pgbase = None
621 mode = None
622 #mbits = None
623 shift = rts
624 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
625 print(result)