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use PRTBL SPR in RADIXMMU
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 x = addr.value >> shift.value
52 return SelectableInt(x,16)
53
54 def NLB(x):
55 """
56 Next Level Base
57 right shifted by 8
58 """
59 return x[4:55]
60
61 def NLS(x):
62 """
63 Next Level Size
64 NLS >= 5
65 """
66 return x[59:63]
67
68 """
69 Get Root Page
70
71 //Accessing 2nd double word of partition table (pate1)
72 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
73 // PTCR Layout
74 // ====================================================
75 // -----------------------------------------------
76 // | /// | PATB | /// | PATS |
77 // -----------------------------------------------
78 // 0 4 51 52 58 59 63
79 // PATB[4:51] holds the base address of the Partition Table,
80 // right shifted by 12 bits.
81 // This is because the address of the Partition base is
82 // 4k aligned. Hence, the lower 12bits, which are always
83 // 0 are ommitted from the PTCR.
84 //
85 // Thus, The Partition Table Base is obtained by (PATB << 12)
86 //
87 // PATS represents the partition table size right-shifted by 12 bits.
88 // The minimal size of the partition table is 4k.
89 // Thus partition table size = (1 << PATS + 12).
90 //
91 // Partition Table
92 // ====================================================
93 // 0 PATE0 63 PATE1 127
94 // |----------------------|----------------------|
95 // | | |
96 // |----------------------|----------------------|
97 // | | |
98 // |----------------------|----------------------|
99 // | | | <-- effLPID
100 // |----------------------|----------------------|
101 // .
102 // .
103 // .
104 // |----------------------|----------------------|
105 // | | |
106 // |----------------------|----------------------|
107 //
108 // The effective LPID forms the index into the Partition Table.
109 //
110 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
111 // corresponding to that partition.
112 //
113 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
114 //
115 // PATE0 Layout
116 // -----------------------------------------------
117 // |1|RTS1|/| RPDB | RTS2 | RPDS |
118 // -----------------------------------------------
119 // 0 1 2 3 4 55 56 58 59 63
120 //
121 // HR[0] : For Radix Page table, first bit should be 1.
122 // RTS1[1:2] : Gives one fragment of the Radix treesize
123 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
124 // RTS = (RTS1 << 3 + RTS2) + 31.
125 //
126 // RPDB[4:55] = Root Page Directory Base.
127 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
128 // Thus, Root page directory size = 1 << (RPDS + 3).
129 // Note: RPDS >= 5.
130 //
131 // PATE1 Layout
132 // -----------------------------------------------
133 // |///| PRTB | // | PRTS |
134 // -----------------------------------------------
135 // 0 3 4 51 52 58 59 63
136 //
137 // PRTB[4:51] = Process Table Base. This is aligned to size.
138 // PRTS[59: 63] = Process Table Size right shifted by 12.
139 // Minimal size of the process table is 4k.
140 // Process Table Size = (1 << PRTS + 12).
141 // Note: PRTS <= 24.
142 //
143 // Computing the size aligned Process Table Base:
144 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
145 // Thus, the lower 12+PRTS bits of table_base will
146 // be zero.
147
148
149 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
150 //
151 // Process Table
152 // ==========================
153 // 0 PRTE0 63 PRTE1 127
154 // |----------------------|----------------------|
155 // | | |
156 // |----------------------|----------------------|
157 // | | |
158 // |----------------------|----------------------|
159 // | | | <-- effPID
160 // |----------------------|----------------------|
161 // .
162 // .
163 // .
164 // |----------------------|----------------------|
165 // | | |
166 // |----------------------|----------------------|
167 //
168 // The effective Process id (PID) forms the index into the Process Table.
169 //
170 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
171 // corresponding to that process
172 //
173 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
174 //
175 // PRTE0 Layout
176 // -----------------------------------------------
177 // |/|RTS1|/| RPDB | RTS2 | RPDS |
178 // -----------------------------------------------
179 // 0 1 2 3 4 55 56 58 59 63
180 //
181 // RTS1[1:2] : Gives one fragment of the Radix treesize
182 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
183 // RTS = (RTS1 << 3 + RTS2) << 31,
184 // since minimal Radix Tree size is 4G.
185 //
186 // RPDB = Root Page Directory Base.
187 // RPDS = Root Page Directory Size right shifted by 3.
188 // Thus, Root page directory size = RPDS << 3.
189 // Note: RPDS >= 5.
190 //
191 // PRTE1 Layout
192 // -----------------------------------------------
193 // | /// |
194 // -----------------------------------------------
195 // 0 63
196 // All bits are reserved.
197
198
199 """
200
201 testmem = {
202
203 0x10000: # PARTITION_TABLE_2 (not implemented yet)
204 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
205 0x800000000100000b,
206
207 0x30000: # RADIX_ROOT_PTE
208 # V = 1 L = 0 NLB = 0x400 NLS = 9
209 0x8000000000040009,
210 0x40000: # RADIX_SECOND_LEVEL
211 # V = 1 L = 1 SW = 0 RPN = 0
212 # R = 1 C = 1 ATT = 0 EAA 0x7
213 0xc000000000000187,
214
215 0x1000000: # PROCESS_TABLE_3
216 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
217 0x40000000000300ad,
218 }
219
220 # this one has a 2nd level RADIX with a RPN of 0x5000
221 testmem2 = {
222
223 0x10000: # PARTITION_TABLE_2 (not implemented yet)
224 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
225 0x800000000100000b,
226
227 0x30000: # RADIX_ROOT_PTE
228 # V = 1 L = 0 NLB = 0x400 NLS = 9
229 0x8000000000040009,
230 0x40000: # RADIX_SECOND_LEVEL
231 # V = 1 L = 1 SW = 0 RPN = 0x5000
232 # R = 1 C = 1 ATT = 0 EAA 0x7
233 0xc000000005000187,
234
235 0x1000000: # PROCESS_TABLE_3
236 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
237 0x40000000000300ad,
238 }
239
240
241 testresult = """
242 prtbl = 1000000
243 DCACHE GET 1000000 PROCESS_TABLE_3
244 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
245 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
246 DCACHE GET 10000 PARTITION_TABLE_2
247 translated done 1 err 0 badtree 0 addr 40000 pte 0
248 """
249
250 # see qemu/target/ppc/mmu-radix64.c for reference
251 class RADIX:
252 def __init__(self, mem, caller):
253 self.mem = mem
254 self.caller = caller
255 if caller is not None:
256 self.dsisr = self.caller.spr["DSISR"]
257 self.dar = self.caller.spr["DAR"]
258 self.pidr = self.caller.spr["PIDR"]
259 self.prtbl = self.caller.spr["PRTBL"]
260 self.msr = self.caller.msr
261
262 # cached page table stuff
263 self.pgtbl0 = 0
264 self.pt0_valid = False
265 self.pgtbl3 = 0
266 self.pt3_valid = False
267
268 def __call__(self, addr, sz):
269 val = self.ld(addr.value, sz, swap=False)
270 print("RADIX memread", addr, sz, val)
271 return SelectableInt(val, sz*8)
272
273 def ld(self, address, width=8, swap=True, check_in_mem=False,
274 instr_fetch=False):
275 print("RADIX: ld from addr 0x%x width %d" % (address, width))
276
277 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
278 if instr_fetch:
279 mode = 'EXECUTE'
280 else:
281 mode = 'LOAD'
282 addr = SelectableInt(address, 64)
283 (shift, mbits, pgbase) = self._decode_prte(addr)
284 #shift = SelectableInt(0, 32)
285
286 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
287
288 # use pte to load from phys address
289 return self.mem.ld(pte.value, width, swap, check_in_mem)
290
291 # XXX set SPRs on error
292
293 # TODO implement
294 def st(self, address, v, width=8, swap=True):
295 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
296
297 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
298 mode = 'STORE'
299 addr = SelectableInt(address, 64)
300 (shift, mbits, pgbase) = self._decode_prte(addr)
301 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
302
303 # use pte to store at phys address
304 return self.mem.st(pte.value, v, width, swap)
305
306 # XXX set SPRs on error
307
308 def memassign(self, addr, sz, val):
309 print("memassign", addr, sz, val)
310 self.st(addr.value, val.value, sz, swap=False)
311
312 def _next_level(self, addr, entry_width, swap, check_in_mem):
313 # implement read access to mmu mem here
314
315 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
316 value = self.mem.ld(addr.value, 8, False, check_in_mem)
317 assert(value is not None, "address lookup %x not found" % addr.value)
318
319 print("addr", hex(addr.value))
320 data = SelectableInt(value, 64) # convert to SelectableInt
321 print("value", hex(value))
322 # index += 1
323 return data;
324
325 def _prtable_lookup(self, prtbl, addr, pid):
326 # v.shift := unsigned('0' & r.prtbl(4 downto 0));
327 shift = prtbl[59:63]
328 print("shift",shift)
329 prtable_addr = self._get_prtable_addr(shift, prtbl, addr, pid)
330 print("prtable_addr",prtable_addr)
331 # TODO check and loop if needed
332
333 assert(prtable_addr==0x1000000)
334 print("fetch data from PROCESS_TABLE_3")
335
336 """
337 if r.addr(63) = '1' then
338 v.pgtbl3 := data;
339 v.pt3_valid := '1';
340 else
341 v.pgtbl0 := data;
342 v.pt0_valid := '1';
343 end if;
344
345 -- The RIC field of the tlbie instruction comes across on the
346 -- sprn bus as bits 2--3. RIC=2 flushes process table caches.
347 if l_in.sprn(3) = '1' then
348 v.pt0_valid := '0';
349 v.pt3_valid := '0';
350 end if;
351
352 if l_in.addr(63) = '0' then
353 pgtbl := r.pgtbl0;
354 pt_valid := r.pt0_valid;
355 else
356 pgtbl := r.pgtbl3;
357 pt_valid := r.pt3_valid;
358 end if;
359
360 if pt_valid = '0' then
361 -- need to fetch process table entry
362 -- set v.shift so we can use finalmask for generating
363 -- the process table entry address
364 v.shift := unsigned('0' & r.prtbl(4 downto 0));
365 v.state := PROC_TBL_READ;
366 elsif mbits = 0 then
367 -- Use RPDS = 0 to disable radix tree walks
368 v.state := RADIX_FINISH;
369 v.invalid := '1';
370 else
371 v.state := SEGMENT_CHECK;
372 end if;
373 """
374
375 return "TODO"
376
377 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
378 """walk tree
379
380 // vaddr 64 Bit
381 // vaddr |-----------------------------------------------------|
382 // | Unused | Used |
383 // |-----------|-----------------------------------------|
384 // | 0000000 | usefulBits = X bits (typically 52) |
385 // |-----------|-----------------------------------------|
386 // | |<--Cursize---->| |
387 // | | Index | |
388 // | | into Page | |
389 // | | Directory | |
390 // |-----------------------------------------------------|
391 // | |
392 // V |
393 // PDE |---------------------------| |
394 // |V|L|//| NLB |///|NLS| |
395 // |---------------------------| |
396 // PDE = Page Directory Entry |
397 // [0] = V = Valid Bit |
398 // [1] = L = Leaf bit. If 0, then |
399 // [4:55] = NLB = Next Level Base |
400 // right shifted by 8 |
401 // [59:63] = NLS = Next Level Size |
402 // | NLS >= 5 |
403 // | V
404 // | |--------------------------|
405 // | | usfulBits = X-Cursize |
406 // | |--------------------------|
407 // |---------------------><--NLS-->| |
408 // | Index | |
409 // | into | |
410 // | PDE | |
411 // |--------------------------|
412 // |
413 // If the next PDE obtained by |
414 // (NLB << 8 + 8 * index) is a |
415 // nonleaf, then repeat the above. |
416 // |
417 // If the next PDE is a leaf, |
418 // then Leaf PDE structure is as |
419 // follows |
420 // |
421 // |
422 // Leaf PDE |
423 // |------------------------------| |----------------|
424 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
425 // |------------------------------| |----------------|
426 // [0] = V = Valid Bit |
427 // [1] = L = Leaf Bit = 1 if leaf |
428 // PDE |
429 // [2] = Sw = Sw bit 0. |
430 // [7:51] = RPN = Real Page Number, V
431 // real_page = RPN << 12 -------------> Logical OR
432 // [52:54] = Sw Bits 1:3 |
433 // [55] = R = Reference |
434 // [56] = C = Change V
435 // [58:59] = Att = Physical Address
436 // 0b00 = Normal Memory
437 // 0b01 = SAO
438 // 0b10 = Non Idenmpotent
439 // 0b11 = Tolerant I/O
440 // [60:63] = Encoded Access
441 // Authority
442 //
443 """
444 # get sprs
445 print("_walk_tree")
446 pidr = self.caller.spr["PIDR"]
447 prtbl = self.caller.spr["PRTBL"]
448 print(pidr)
449 print(prtbl)
450 p = addr[55:63]
451 print("last 8 bits ----------")
452 print
453
454 # get address of root entry
455 shift = selectconcat(SelectableInt(0,1), prtbl[58:63]) # TODO verify
456 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
457 print("starting with prtable, addr_next",addr_next)
458
459 assert(addr_next.bits == 64)
460 assert(addr_next.value == 0x1000000) #TODO
461
462 addr_next = SelectableInt(0x30000,64) # radix root for testing
463
464 # walk tree starts on prtbl
465 while True:
466 print("nextlevel----------------------------")
467 # read an entry
468 swap = False
469 check_in_mem = False
470 entry_width = 8
471
472 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
473 valid = rpte_valid(data)
474 leaf = rpte_leaf(data)
475
476 print(" valid, leaf", valid, leaf)
477 if not valid:
478 return "invalid" # TODO: return error
479 if leaf:
480 print ("is leaf, checking perms")
481 ok = self._check_perms(data, priv, mode)
482 if ok == True: # data was ok, found phys address, return it?
483 paddr = self._get_pte(addrsh, addr, data)
484 print (" phys addr", hex(paddr.value))
485 return paddr
486 return ok # return the error code
487 else:
488 newlookup = self._new_lookup(data, mbits, shift)
489 if newlookup == 'badtree':
490 return newlookup
491 shift, mask, pgbase = newlookup
492 print (" next level", shift, mask, pgbase)
493 shift = SelectableInt(shift.value,16) #THIS is wrong !!!
494 print("calling _get_pgtable_addr")
495 print(mask) #SelectableInt(value=0x9, bits=4)
496 print(pgbase) #SelectableInt(value=0x40000, bits=56)
497 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
498 pgbase = SelectableInt(pgbase.value, 64)
499 addrsh = addrshift(addr,shift)
500 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
501 print("addr_next",addr_next)
502 print("addrsh",addrsh)
503
504 def _new_lookup(self, data, mbits, shift):
505 """
506 mbits := unsigned('0' & data(4 downto 0));
507 if mbits < 5 or mbits > 16 or mbits > r.shift then
508 v.state := RADIX_FINISH;
509 v.badtree := '1'; -- throw error
510 else
511 v.shift := v.shift - mbits;
512 v.mask_size := mbits(4 downto 0);
513 v.pgbase := data(55 downto 8) & x"00"; NLB?
514 v.state := RADIX_LOOKUP; --> next level
515 end if;
516 """
517 mbits = data[59:64]
518 print("mbits=", mbits)
519 if mbits < 5 or mbits > 16: #fixme compare with r.shift
520 print("badtree")
521 return "badtree"
522 # reduce shift (has to be done at same bitwidth)
523 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
524 mask_size = mbits[1:5] # get 4 LSBs
525 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
526 return shift, mask_size, pgbase
527
528 def _decode_prte(self, data):
529 """PRTE0 Layout
530 -----------------------------------------------
531 |/|RTS1|/| RPDB | RTS2 | RPDS |
532 -----------------------------------------------
533 0 1 2 3 4 55 56 58 59 63
534 """
535 # note that SelectableInt does big-endian! so the indices
536 # below *directly* match the spec, unlike microwatt which
537 # has to turn them around (to LE)
538 zero = SelectableInt(0, 1)
539 rts = selectconcat(zero,
540 data[56:59], # RTS2
541 data[1:3], # RTS1
542 )
543 masksize = data[59:64] # RPDS
544 mbits = selectconcat(zero, masksize)
545 pgbase = selectconcat(data[8:56], # part of RPDB
546 SelectableInt(0, 16),)
547
548 return (rts, mbits, pgbase)
549
550 def _segment_check(self, addr, mbits, shift):
551 """checks segment valid
552 mbits := '0' & r.mask_size;
553 v.shift := r.shift + (31 - 12) - mbits;
554 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
555 if r.addr(63) /= r.addr(62) or nonzero = '1' then
556 v.state := RADIX_FINISH;
557 v.segerror := '1';
558 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
559 v.state := RADIX_FINISH;
560 v.badtree := '1';
561 else
562 v.state := RADIX_LOOKUP;
563 """
564 # note that SelectableInt does big-endian! so the indices
565 # below *directly* match the spec, unlike microwatt which
566 # has to turn them around (to LE)
567 mask = genmask(shift, 44)
568 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
569 print ("RADIX _segment_check nonzero", bin(nonzero.value))
570 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
571 if addr[0] != addr[1] or nonzero != 0:
572 return "segerror"
573 limit = shift + (31 - 12)
574 if mbits < 5 or mbits > 16 or mbits > limit:
575 return "badtree"
576 new_shift = shift + (31 - 12) - mbits
577 return new_shift
578
579 def _check_perms(self, data, priv, mode):
580 """check page permissions
581 // Leaf PDE |
582 // |------------------------------| |----------------|
583 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
584 // |------------------------------| |----------------|
585 // [0] = V = Valid Bit |
586 // [1] = L = Leaf Bit = 1 if leaf |
587 // PDE |
588 // [2] = Sw = Sw bit 0. |
589 // [7:51] = RPN = Real Page Number, V
590 // real_page = RPN << 12 -------------> Logical OR
591 // [52:54] = Sw Bits 1:3 |
592 // [55] = R = Reference |
593 // [56] = C = Change V
594 // [58:59] = Att = Physical Address
595 // 0b00 = Normal Memory
596 // 0b01 = SAO
597 // 0b10 = Non Idenmpotent
598 // 0b11 = Tolerant I/O
599 // [60:63] = Encoded Access
600 // Authority
601 //
602 -- test leaf bit
603 -- check permissions and RC bits
604 perm_ok := '0';
605 if r.priv = '1' or data(3) = '0' then
606 if r.iside = '0' then
607 perm_ok := data(1) or (data(2) and not r.store);
608 else
609 -- no IAMR, so no KUEP support for now
610 -- deny execute permission if cache inhibited
611 perm_ok := data(0) and not data(5);
612 end if;
613 end if;
614 rc_ok := data(8) and (data(7) or not r.store);
615 if perm_ok = '1' and rc_ok = '1' then
616 v.state := RADIX_LOAD_TLB;
617 else
618 v.state := RADIX_FINISH;
619 v.perm_err := not perm_ok;
620 -- permission error takes precedence over RC error
621 v.rc_error := perm_ok;
622 end if;
623 """
624 # decode mode into something that matches microwatt equivalent code
625 instr_fetch, store = 0, 0
626 if mode == 'STORE':
627 store = 1
628 if mode == 'EXECUTE':
629 inst_fetch = 1
630
631 # check permissions and RC bits
632 perm_ok = 0
633 if priv == 1 or data[60] == 0:
634 if instr_fetch == 0:
635 perm_ok = data[62] | (data[61] & (store == 0))
636 # no IAMR, so no KUEP support for now
637 # deny execute permission if cache inhibited
638 perm_ok = data[63] & ~data[58]
639 rc_ok = data[55] & (data[56] | (store == 0))
640 if perm_ok == 1 and rc_ok == 1:
641 return True
642
643 return "perm_err" if perm_ok == 0 else "rc_err"
644
645 def _get_prtable_addr(self, shift, prtbl, addr, pid):
646 """
647 if r.addr(63) = '1' then
648 effpid := x"00000000";
649 else
650 effpid := r.pid;
651 end if;
652 x"00" & r.prtbl(55 downto 36) &
653 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
654 (effpid(31 downto 8) and finalmask(23 downto 0))) &
655 effpid(7 downto 0) & "0000";
656 """
657 print ("_get_prtable_addr", shift, prtbl, addr, pid)
658 finalmask = genmask(shift, 44)
659 finalmask24 = finalmask[20:44]
660 if addr[0].value == 1:
661 effpid = SelectableInt(0, 32)
662 else:
663 effpid = pid #self.pid # TODO, check on this
664 zero8 = SelectableInt(0, 8)
665 zero4 = SelectableInt(0, 4)
666 res = selectconcat(zero8,
667 prtbl[8:28], #
668 (prtbl[28:52] & ~finalmask24) | #
669 (effpid[0:24] & finalmask24), #
670 effpid[24:32],
671 zero4
672 )
673 return res
674
675 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
676 """
677 x"00" & r.pgbase(55 downto 19) &
678 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
679 "000";
680 """
681 mask16 = genmask(mask_size+5, 16)
682 zero8 = SelectableInt(0, 8)
683 zero3 = SelectableInt(0, 3)
684 res = selectconcat(zero8,
685 pgbase[8:45], #
686 (pgbase[45:61] & ~mask16) | #
687 (addrsh & mask16), #
688 zero3
689 )
690 return res
691
692 def _get_pte(self, shift, addr, pde):
693 """
694 x"00" &
695 ((r.pde(55 downto 12) and not finalmask) or
696 (r.addr(55 downto 12) and finalmask))
697 & r.pde(11 downto 0);
698 """
699 shift.value = 12
700 finalmask = genmask(shift, 44)
701 zero8 = SelectableInt(0, 8)
702 rpn = pde[8:52] # RPN = Real Page Number
703 abits = addr[8:52] # non-masked address bits
704 print(" get_pte RPN", hex(rpn.value))
705 print(" abits", hex(abits.value))
706 print(" shift", shift.value)
707 print(" finalmask", bin(finalmask.value))
708 res = selectconcat(zero8,
709 (rpn & ~finalmask) | #
710 (abits & finalmask), #
711 addr[52:64],
712 )
713 return res
714
715 class TestRadixMMU(unittest.TestCase):
716
717 def test_genmask(self):
718 shift = SelectableInt(5, 6)
719 mask = genmask(shift, 43)
720 print (" mask", bin(mask.value))
721
722 self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
723
724 def test_get_pgtable_addr(self):
725
726 mem = None
727 caller = None
728 dut = RADIX(mem, caller)
729
730 mask_size=4
731 pgbase = SelectableInt(0,64)
732 addrsh = SelectableInt(0,16)
733 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
734 print("ret=", ret)
735 self.assertEqual(ret, 0, "pgtbl_addr should be 0")
736
737 def test_prtable_lookup(self):
738
739 mem = None
740 caller = None
741 dut = RADIX(mem, caller)
742
743 prtbl = SelectableInt(0x1000000,64)
744 addr = SelectableInt(0, 64)
745 pid = SelectableInt(0, 64)
746 ret = dut._prtable_lookup(prtbl, addr, pid)
747
748 def test_walk_tree_1(self):
749
750 # test address as in
751 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
752 testaddr = 0x1000
753 expected = 0x1000
754
755 # starting prtbl
756 prtbl = 0x1000000
757
758 # set up dummy minimal ISACaller
759 spr = {'DSISR': SelectableInt(0, 64),
760 'DAR': SelectableInt(0, 64),
761 'PIDR': SelectableInt(0, 64),
762 'PRTBL': SelectableInt(prtbl, 64)
763 }
764 # set problem state == 0 (other unit tests, set to 1)
765 msr = SelectableInt(0, 64)
766 msr[MSRb.PR] = 0
767 class ISACaller: pass
768 caller = ISACaller()
769 caller.spr = spr
770 caller.msr = msr
771
772 shift = SelectableInt(5, 6)
773 mask = genmask(shift, 43)
774 print (" mask", bin(mask.value))
775
776 mem = Mem(row_bytes=8, initial_mem=testmem)
777 mem = RADIX(mem, caller)
778 # -----------------------------------------------
779 # |/|RTS1|/| RPDB | RTS2 | RPDS |
780 # -----------------------------------------------
781 # |0|1 2|3|4 55|56 58|59 63|
782 data = SelectableInt(0, 64)
783 data[1:3] = 0b01
784 data[56:59] = 0b11
785 data[59:64] = 0b01101 # mask
786 data[55] = 1
787 (rts, mbits, pgbase) = mem._decode_prte(data)
788 print (" rts", bin(rts.value), rts.bits)
789 print (" mbits", bin(mbits.value), mbits.bits)
790 print (" pgbase", hex(pgbase.value), pgbase.bits)
791 addr = SelectableInt(0x1000, 64)
792 check = mem._segment_check(addr, mbits, shift)
793 print (" segment check", check)
794
795 print("walking tree")
796 addr = SelectableInt(testaddr,64)
797 # pgbase = None
798 mode = None
799 #mbits = None
800 shift = rts
801 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
802 print(" walking tree result", result)
803 print("should be", testresult)
804 self.assertEqual(result.value, expected,
805 "expected 0x%x got 0x%x" % (expected,
806 result.value))
807
808
809 def test_walk_tree_2(self):
810
811 # test address slightly different
812 testaddr = 0x1101
813 expected = 0x5001101
814
815 # starting prtbl
816 prtbl = 0x1000000
817
818 # set up dummy minimal ISACaller
819 spr = {'DSISR': SelectableInt(0, 64),
820 'DAR': SelectableInt(0, 64),
821 'PIDR': SelectableInt(0, 64),
822 'PRTBL': SelectableInt(prtbl, 64)
823 }
824 # set problem state == 0 (other unit tests, set to 1)
825 msr = SelectableInt(0, 64)
826 msr[MSRb.PR] = 0
827 class ISACaller: pass
828 caller = ISACaller()
829 caller.spr = spr
830 caller.msr = msr
831
832 shift = SelectableInt(5, 6)
833 mask = genmask(shift, 43)
834 print (" mask", bin(mask.value))
835
836 mem = Mem(row_bytes=8, initial_mem=testmem2)
837 mem = RADIX(mem, caller)
838 # -----------------------------------------------
839 # |/|RTS1|/| RPDB | RTS2 | RPDS |
840 # -----------------------------------------------
841 # |0|1 2|3|4 55|56 58|59 63|
842 data = SelectableInt(0, 64)
843 data[1:3] = 0b01
844 data[56:59] = 0b11
845 data[59:64] = 0b01101 # mask
846 data[55] = 1
847 (rts, mbits, pgbase) = mem._decode_prte(data)
848 print (" rts", bin(rts.value), rts.bits)
849 print (" mbits", bin(mbits.value), mbits.bits)
850 print (" pgbase", hex(pgbase.value), pgbase.bits)
851 addr = SelectableInt(0x1000, 64)
852 check = mem._segment_check(addr, mbits, shift)
853 print (" segment check", check)
854
855 print("walking tree")
856 addr = SelectableInt(testaddr,64)
857 # pgbase = None
858 mode = None
859 #mbits = None
860 shift = rts
861 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
862 print(" walking tree result", result)
863 print("should be", testresult)
864 self.assertEqual(result.value, expected,
865 "expected 0x%x got 0x%x" % (expected,
866 result.value))
867
868
869 if __name__ == '__main__':
870 unittest.main()