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correct segment check (off by one in LE/BE convert
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 x = addr.value >> shift.value
52 return SelectableInt(x,16)
53
54 def NLB(x):
55 """
56 Next Level Base
57 right shifted by 8
58 """
59 return x[4:55]
60
61 def NLS(x):
62 """
63 Next Level Size
64 NLS >= 5
65 """
66 return x[59:63]
67
68 """
69 Get Root Page
70
71 //Accessing 2nd double word of partition table (pate1)
72 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
73 // PTCR Layout
74 // ====================================================
75 // -----------------------------------------------
76 // | /// | PATB | /// | PATS |
77 // -----------------------------------------------
78 // 0 4 51 52 58 59 63
79 // PATB[4:51] holds the base address of the Partition Table,
80 // right shifted by 12 bits.
81 // This is because the address of the Partition base is
82 // 4k aligned. Hence, the lower 12bits, which are always
83 // 0 are ommitted from the PTCR.
84 //
85 // Thus, The Partition Table Base is obtained by (PATB << 12)
86 //
87 // PATS represents the partition table size right-shifted by 12 bits.
88 // The minimal size of the partition table is 4k.
89 // Thus partition table size = (1 << PATS + 12).
90 //
91 // Partition Table
92 // ====================================================
93 // 0 PATE0 63 PATE1 127
94 // |----------------------|----------------------|
95 // | | |
96 // |----------------------|----------------------|
97 // | | |
98 // |----------------------|----------------------|
99 // | | | <-- effLPID
100 // |----------------------|----------------------|
101 // .
102 // .
103 // .
104 // |----------------------|----------------------|
105 // | | |
106 // |----------------------|----------------------|
107 //
108 // The effective LPID forms the index into the Partition Table.
109 //
110 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
111 // corresponding to that partition.
112 //
113 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
114 //
115 // PATE0 Layout
116 // -----------------------------------------------
117 // |1|RTS1|/| RPDB | RTS2 | RPDS |
118 // -----------------------------------------------
119 // 0 1 2 3 4 55 56 58 59 63
120 //
121 // HR[0] : For Radix Page table, first bit should be 1.
122 // RTS1[1:2] : Gives one fragment of the Radix treesize
123 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
124 // RTS = (RTS1 << 3 + RTS2) + 31.
125 //
126 // RPDB[4:55] = Root Page Directory Base.
127 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
128 // Thus, Root page directory size = 1 << (RPDS + 3).
129 // Note: RPDS >= 5.
130 //
131 // PATE1 Layout
132 // -----------------------------------------------
133 // |///| PRTB | // | PRTS |
134 // -----------------------------------------------
135 // 0 3 4 51 52 58 59 63
136 //
137 // PRTB[4:51] = Process Table Base. This is aligned to size.
138 // PRTS[59: 63] = Process Table Size right shifted by 12.
139 // Minimal size of the process table is 4k.
140 // Process Table Size = (1 << PRTS + 12).
141 // Note: PRTS <= 24.
142 //
143 // Computing the size aligned Process Table Base:
144 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
145 // Thus, the lower 12+PRTS bits of table_base will
146 // be zero.
147
148
149 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
150 //
151 // Process Table
152 // ==========================
153 // 0 PRTE0 63 PRTE1 127
154 // |----------------------|----------------------|
155 // | | |
156 // |----------------------|----------------------|
157 // | | |
158 // |----------------------|----------------------|
159 // | | | <-- effPID
160 // |----------------------|----------------------|
161 // .
162 // .
163 // .
164 // |----------------------|----------------------|
165 // | | |
166 // |----------------------|----------------------|
167 //
168 // The effective Process id (PID) forms the index into the Process Table.
169 //
170 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
171 // corresponding to that process
172 //
173 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
174 //
175 // PRTE0 Layout
176 // -----------------------------------------------
177 // |/|RTS1|/| RPDB | RTS2 | RPDS |
178 // -----------------------------------------------
179 // 0 1 2 3 4 55 56 58 59 63
180 //
181 // RTS1[1:2] : Gives one fragment of the Radix treesize
182 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
183 // RTS = (RTS1 << 3 + RTS2) << 31,
184 // since minimal Radix Tree size is 4G.
185 //
186 // RPDB = Root Page Directory Base.
187 // RPDS = Root Page Directory Size right shifted by 3.
188 // Thus, Root page directory size = RPDS << 3.
189 // Note: RPDS >= 5.
190 //
191 // PRTE1 Layout
192 // -----------------------------------------------
193 // | /// |
194 // -----------------------------------------------
195 // 0 63
196 // All bits are reserved.
197
198
199 """
200
201 testaddr = 0x10000
202 testmem = {
203
204 0x10000: # PARTITION_TABLE_2 (not implemented yet)
205 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
206 0x800000000100000b,
207
208 0x30000: # RADIX_ROOT_PTE
209 # V = 1 L = 0 NLB = 0x400 NLS = 9
210 0x8000000000040009,
211 0x40000: # RADIX_SECOND_LEVEL
212 # V = 1 L = 1 SW = 0 RPN = 0
213 # R = 1 C = 1 ATT = 0 EAA 0x7
214 0xc000000000000187,
215
216 0x1000000: # PROCESS_TABLE_3
217 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
218 0x40000000000300ad,
219 }
220
221
222 testresult = """
223 prtbl = 1000000
224 DCACHE GET 1000000 PROCESS_TABLE_3
225 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
226 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
227 DCACHE GET 10000 PARTITION_TABLE_2
228 translated done 1 err 0 badtree 0 addr 40000 pte 0
229 """
230
231 # see qemu/target/ppc/mmu-radix64.c for reference
232 class RADIX:
233 def __init__(self, mem, caller):
234 self.mem = mem
235 self.caller = caller
236 if caller is not None:
237 self.dsisr = self.caller.spr["DSISR"]
238 self.dar = self.caller.spr["DAR"]
239 self.pidr = self.caller.spr["PIDR"]
240 self.prtbl = self.caller.spr["PRTBL"]
241 self.msr = self.caller.msr
242
243 # cached page table stuff
244 self.pgtbl0 = 0
245 self.pt0_valid = False
246 self.pgtbl3 = 0
247 self.pt3_valid = False
248
249 def __call__(self, addr, sz):
250 val = self.ld(addr.value, sz, swap=False)
251 print("RADIX memread", addr, sz, val)
252 return SelectableInt(val, sz*8)
253
254 def ld(self, address, width=8, swap=True, check_in_mem=False,
255 instr_fetch=False):
256 print("RADIX: ld from addr 0x%x width %d" % (address, width))
257
258 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
259 if instr_fetch:
260 mode = 'EXECUTE'
261 else:
262 mode = 'LOAD'
263 addr = SelectableInt(address, 64)
264 (shift, mbits, pgbase) = self._decode_prte(addr)
265 #shift = SelectableInt(0, 32)
266
267 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
268 # use pte to caclculate phys address
269 return self.mem.ld(address, width, swap, check_in_mem)
270
271 # XXX set SPRs on error
272
273 # TODO implement
274 def st(self, address, v, width=8, swap=True):
275 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
276
277 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
278 mode = 'STORE'
279 addr = SelectableInt(address, 64)
280 (shift, mbits, pgbase) = self._decode_prte(addr)
281 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
282
283 # use pte to caclculate phys address (addr)
284 return self.mem.st(addr.value, v, width, swap)
285
286 # XXX set SPRs on error
287
288 def memassign(self, addr, sz, val):
289 print("memassign", addr, sz, val)
290 self.st(addr.value, val.value, sz, swap=False)
291
292 def _next_level(self, addr, entry_width, swap, check_in_mem):
293 # implement read access to mmu mem here
294
295 value = 0
296 if addr.value in testmem:
297 value = testmem[addr.value]
298 else:
299 print("not found")
300
301 ##value = self.mem.ld(addr.value, entry_width, swap, check_in_mem)
302 print("addr", hex(addr.value))
303 data = SelectableInt(value, 64) # convert to SelectableInt
304 print("value", hex(value))
305 # index += 1
306 return data;
307
308 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
309 """walk tree
310
311 // vaddr 64 Bit
312 // vaddr |-----------------------------------------------------|
313 // | Unused | Used |
314 // |-----------|-----------------------------------------|
315 // | 0000000 | usefulBits = X bits (typically 52) |
316 // |-----------|-----------------------------------------|
317 // | |<--Cursize---->| |
318 // | | Index | |
319 // | | into Page | |
320 // | | Directory | |
321 // |-----------------------------------------------------|
322 // | |
323 // V |
324 // PDE |---------------------------| |
325 // |V|L|//| NLB |///|NLS| |
326 // |---------------------------| |
327 // PDE = Page Directory Entry |
328 // [0] = V = Valid Bit |
329 // [1] = L = Leaf bit. If 0, then |
330 // [4:55] = NLB = Next Level Base |
331 // right shifted by 8 |
332 // [59:63] = NLS = Next Level Size |
333 // | NLS >= 5 |
334 // | V
335 // | |--------------------------|
336 // | | usfulBits = X-Cursize |
337 // | |--------------------------|
338 // |---------------------><--NLS-->| |
339 // | Index | |
340 // | into | |
341 // | PDE | |
342 // |--------------------------|
343 // |
344 // If the next PDE obtained by |
345 // (NLB << 8 + 8 * index) is a |
346 // nonleaf, then repeat the above. |
347 // |
348 // If the next PDE is a leaf, |
349 // then Leaf PDE structure is as |
350 // follows |
351 // |
352 // |
353 // Leaf PDE |
354 // |------------------------------| |----------------|
355 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
356 // |------------------------------| |----------------|
357 // [0] = V = Valid Bit |
358 // [1] = L = Leaf Bit = 1 if leaf |
359 // PDE |
360 // [2] = Sw = Sw bit 0. |
361 // [7:51] = RPN = Real Page Number, V
362 // real_page = RPN << 12 -------------> Logical OR
363 // [52:54] = Sw Bits 1:3 |
364 // [55] = R = Reference |
365 // [56] = C = Change V
366 // [58:59] = Att = Physical Address
367 // 0b00 = Normal Memory
368 // 0b01 = SAO
369 // 0b10 = Non Idenmpotent
370 // 0b11 = Tolerant I/O
371 // [60:63] = Encoded Access
372 // Authority
373 //
374 """
375 # get sprs
376 print("_walk_tree")
377 pidr = self.caller.spr["PIDR"]
378 prtbl = self.caller.spr["PRTBL"]
379 print(pidr)
380 print(prtbl)
381 p = addr[55:63]
382 print("last 8 bits ----------")
383 print
384
385 prtbl = SelectableInt(0x1000000,64) #FIXME do not hardcode
386
387 # get address of root entry
388 shift = selectconcat(SelectableInt(0,1),prtbl[58:63]) # TODO verify
389 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
390 print("starting with addr_next",addr_next)
391
392 assert(addr_next.bits==64)
393 assert(addr_next.value==0x1000000) #TODO
394
395 addr_next = SelectableInt(0x30000,64) # radix root for testing
396
397 # walk tree starts on prtbl
398 while True:
399 print("nextlevel----------------------------")
400 # read an entry
401 swap = False
402 check_in_mem = False
403 entry_width = 8
404
405 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
406 valid = rpte_valid(data)
407 leaf = rpte_leaf(data)
408
409 print(" valid, leaf", valid, leaf)
410 if not valid:
411 return "invalid" # TODO: return error
412 if leaf:
413 ok = self._check_perms(data, priv, mode)
414 if ok == True: # data was ok, found phys address, return it?
415 return addr_next
416 return ok # return the error code
417 else:
418 newlookup = self._new_lookup(data, mbits, shift)
419 if newlookup == 'badtree':
420 return newlookup
421 shift, mask, pgbase = newlookup
422 print (" next level", shift, mask, pgbase)
423 shift = SelectableInt(shift.value,16) #THIS is wrong !!!
424 print("calling _get_pgtable_addr")
425 print(mask) #SelectableInt(value=0x9, bits=4)
426 print(pgbase) #SelectableInt(value=0x40000, bits=56)
427 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
428 pgbase = SelectableInt(pgbase.value,64)
429 addrsh = addrshift(addr,shift)
430 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
431 print("addr_next",addr_next)
432 print("addrsh",addrsh)
433
434 def _new_lookup(self, data, mbits, shift):
435 """
436 mbits := unsigned('0' & data(4 downto 0));
437 if mbits < 5 or mbits > 16 or mbits > r.shift then
438 v.state := RADIX_FINISH;
439 v.badtree := '1'; -- throw error
440 else
441 v.shift := v.shift - mbits;
442 v.mask_size := mbits(4 downto 0);
443 v.pgbase := data(55 downto 8) & x"00"; NLB?
444 v.state := RADIX_LOOKUP; --> next level
445 end if;
446 """
447 mbits = data[59:64]
448 print("mbits=", mbits)
449 if mbits < 5 or mbits > 16: #fixme compare with r.shift
450 print("badtree")
451 return "badtree"
452 # reduce shift (has to be done at same bitwidth)
453 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
454 mask_size = mbits[1:5] # get 4 LSBs
455 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
456 return shift, mask_size, pgbase
457
458 def _decode_prte(self, data):
459 """PRTE0 Layout
460 -----------------------------------------------
461 |/|RTS1|/| RPDB | RTS2 | RPDS |
462 -----------------------------------------------
463 0 1 2 3 4 55 56 58 59 63
464 """
465 # note that SelectableInt does big-endian! so the indices
466 # below *directly* match the spec, unlike microwatt which
467 # has to turn them around (to LE)
468 zero = SelectableInt(0, 1)
469 rts = selectconcat(zero,
470 data[56:59], # RTS2
471 data[1:3], # RTS1
472 )
473 masksize = data[59:64] # RPDS
474 mbits = selectconcat(zero, masksize)
475 pgbase = selectconcat(data[8:56], # part of RPDB
476 SelectableInt(0, 16),)
477
478 return (rts, mbits, pgbase)
479
480 def _segment_check(self, addr, mbits, shift):
481 """checks segment valid
482 mbits := '0' & r.mask_size;
483 v.shift := r.shift + (31 - 12) - mbits;
484 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
485 if r.addr(63) /= r.addr(62) or nonzero = '1' then
486 v.state := RADIX_FINISH;
487 v.segerror := '1';
488 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
489 v.state := RADIX_FINISH;
490 v.badtree := '1';
491 else
492 v.state := RADIX_LOOKUP;
493 """
494 # note that SelectableInt does big-endian! so the indices
495 # below *directly* match the spec, unlike microwatt which
496 # has to turn them around (to LE)
497 mask = genmask(shift, 44)
498 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
499 print ("RADIX _segment_check nonzero", bin(nonzero.value))
500 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
501 if addr[0] != addr[1] or nonzero != 0:
502 return "segerror"
503 limit = shift + (31 - 12)
504 if mbits < 5 or mbits > 16 or mbits > limit:
505 return "badtree"
506 new_shift = shift + (31 - 12) - mbits
507 return new_shift
508
509 def _check_perms(self, data, priv, mode):
510 """check page permissions
511 // Leaf PDE |
512 // |------------------------------| |----------------|
513 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
514 // |------------------------------| |----------------|
515 // [0] = V = Valid Bit |
516 // [1] = L = Leaf Bit = 1 if leaf |
517 // PDE |
518 // [2] = Sw = Sw bit 0. |
519 // [7:51] = RPN = Real Page Number, V
520 // real_page = RPN << 12 -------------> Logical OR
521 // [52:54] = Sw Bits 1:3 |
522 // [55] = R = Reference |
523 // [56] = C = Change V
524 // [58:59] = Att = Physical Address
525 // 0b00 = Normal Memory
526 // 0b01 = SAO
527 // 0b10 = Non Idenmpotent
528 // 0b11 = Tolerant I/O
529 // [60:63] = Encoded Access
530 // Authority
531 //
532 -- test leaf bit
533 -- check permissions and RC bits
534 perm_ok := '0';
535 if r.priv = '1' or data(3) = '0' then
536 if r.iside = '0' then
537 perm_ok := data(1) or (data(2) and not r.store);
538 else
539 -- no IAMR, so no KUEP support for now
540 -- deny execute permission if cache inhibited
541 perm_ok := data(0) and not data(5);
542 end if;
543 end if;
544 rc_ok := data(8) and (data(7) or not r.store);
545 if perm_ok = '1' and rc_ok = '1' then
546 v.state := RADIX_LOAD_TLB;
547 else
548 v.state := RADIX_FINISH;
549 v.perm_err := not perm_ok;
550 -- permission error takes precedence over RC error
551 v.rc_error := perm_ok;
552 end if;
553 """
554 # decode mode into something that matches microwatt equivalent code
555 instr_fetch, store = 0, 0
556 if mode == 'STORE':
557 store = 1
558 if mode == 'EXECUTE':
559 inst_fetch = 1
560
561 # check permissions and RC bits
562 perm_ok = 0
563 if priv == 1 or data[60] == 0:
564 if instr_fetch == 0:
565 perm_ok = data[62] | (data[61] & (store == 0))
566 # no IAMR, so no KUEP support for now
567 # deny execute permission if cache inhibited
568 perm_ok = data[63] & ~data[58]
569 rc_ok = data[55] & (data[56] | (store == 0))
570 if perm_ok == 1 and rc_ok == 1:
571 return True
572
573 return "perm_err" if perm_ok == 0 else "rc_err"
574
575 def _get_prtable_addr(self, shift, prtbl, addr, pid):
576 """
577 if r.addr(63) = '1' then
578 effpid := x"00000000";
579 else
580 effpid := r.pid;
581 end if;
582 x"00" & r.prtbl(55 downto 36) &
583 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
584 (effpid(31 downto 8) and finalmask(23 downto 0))) &
585 effpid(7 downto 0) & "0000";
586 """
587 print ("_get_prtable_addr_", shift, prtbl, addr, pid)
588 finalmask = genmask(shift, 44)
589 finalmask24 = finalmask[20:44]
590 if addr[0].value == 1:
591 effpid = SelectableInt(0, 32)
592 else:
593 effpid = pid #self.pid # TODO, check on this
594 zero8 = SelectableInt(0, 8)
595 zero4 = SelectableInt(0, 4)
596 res = selectconcat(zero8,
597 prtbl[8:28], #
598 (prtbl[28:52] & ~finalmask24) | #
599 (effpid[0:24] & finalmask24), #
600 effpid[24:32],
601 zero4
602 )
603 return res
604
605 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
606 """
607 x"00" & r.pgbase(55 downto 19) &
608 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
609 "000";
610 """
611 mask16 = genmask(mask_size+5, 16)
612 zero8 = SelectableInt(0, 8)
613 zero3 = SelectableInt(0, 3)
614 res = selectconcat(zero8,
615 pgbase[8:45], #
616 (pgbase[45:61] & ~mask16) | #
617 (addrsh & mask16), #
618 zero3
619 )
620 return res
621
622 def _get_pte(self, shift, addr, pde):
623 """
624 x"00" &
625 ((r.pde(55 downto 12) and not finalmask) or
626 (r.addr(55 downto 12) and finalmask))
627 & r.pde(11 downto 0);
628 """
629 finalmask = genmask(shift, 44)
630 zero8 = SelectableInt(0, 8)
631 res = selectconcat(zero8,
632 (pde[8:52] & ~finalmask) | #
633 (addr[8:52] & finalmask), #
634 pde[52:64],
635 )
636 return res
637
638 class TestRadixMMU(unittest.TestCase):
639
640 def test_genmask(self):
641 shift = SelectableInt(5, 6)
642 mask = genmask(shift, 43)
643 print (" mask", bin(mask.value))
644
645 self.assertEqual(sum([1, 2, 3]), 6, "Should be 6")
646
647 def test_get_pgtable_addr(self):
648
649 mem = None
650 caller = None
651 dut = RADIX(mem, caller)
652
653 mask_size=4
654 pgbase = SelectableInt(0,64)
655 addrsh = SelectableInt(0,16)
656 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
657 print("ret=",ret)
658 assert(ret==0)
659
660 def test_walk_tree(self):
661 # set up dummy minimal ISACaller
662 spr = {'DSISR': SelectableInt(0, 64),
663 'DAR': SelectableInt(0, 64),
664 'PIDR': SelectableInt(0, 64),
665 'PRTBL': SelectableInt(0, 64)
666 }
667 # set problem state == 0 (other unit tests, set to 1)
668 msr = SelectableInt(0, 64)
669 msr[MSRb.PR] = 0
670 class ISACaller: pass
671 caller = ISACaller()
672 caller.spr = spr
673 caller.msr = msr
674
675 shift = SelectableInt(5, 6)
676 mask = genmask(shift, 43)
677 print (" mask", bin(mask.value))
678
679 mem = Mem(row_bytes=8)
680 mem = RADIX(mem, caller)
681 # -----------------------------------------------
682 # |/|RTS1|/| RPDB | RTS2 | RPDS |
683 # -----------------------------------------------
684 # |0|1 2|3|4 55|56 58|59 63|
685 data = SelectableInt(0, 64)
686 data[1:3] = 0b01
687 data[56:59] = 0b11
688 data[59:64] = 0b01101 # mask
689 data[55] = 1
690 (rts, mbits, pgbase) = mem._decode_prte(data)
691 print (" rts", bin(rts.value), rts.bits)
692 print (" mbits", bin(mbits.value), mbits.bits)
693 print (" pgbase", hex(pgbase.value), pgbase.bits)
694 addr = SelectableInt(0x1000, 64)
695 check = mem._segment_check(addr, mbits, shift)
696 print (" segment check", check)
697
698 print("walking tree")
699 addr = SelectableInt(testaddr,64)
700 # pgbase = None
701 mode = None
702 #mbits = None
703 shift = rts
704 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
705 print(" walking tree result", result)
706 print("should be",testresult)
707
708
709 if __name__ == '__main__':
710 unittest.main()