add fu logical_input_record.py
[soc.git] / src / soc / decoder / isa / sprset.patch
1 --- sprset.py.orig 2020-05-16 14:04:43.548374778 -0400
2 +++ sprset.py 2020-05-16 14:34:05.369303775 -0400
3 @@ -54,7 +54,7 @@
4 n = i
5 count = count + 1
6 if eq(count, 1):
7 - CR[4 * n + 32:4 * n + 35 + 1] = RS[4 * n + 32:4 * n + 35 + 1]
8 + CR.si[4 * n + 32:4 * n + 35 + 1] = RS[4 * n + 32:4 * n + 35 + 1]
9 else:
10 CR = undefined
11 return (CR,)
12 @@ -78,7 +78,7 @@
13 count = count + 1
14 if eq(count, 1):
15 RT = concat(0, repeat=64)
16 - RT[4 * n + 32:4 * n + 35 + 1] = CR[4 * n + 32:4 * n + 35 + 1]
17 + RT[4 * n + 32:4 * n + 35 + 1] = CR.si[4 * n + 32:4 * n + 35 + 1]
18 return (RT, CR,)
19
20 @inject()