src/soc/decoder/isa/test_caller_radix.py

   1 from nmigen import Module, Signal
   2 #from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, inject, RADIX
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import run_tst
  14
  15 from copy import deepcopy
  16
  17 testmem = {
  18
  19            0x10000:    # PARTITION_TABLE_2 (not implemented yet)
  20                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
  21            0x800000000100000b,
  22
  23            0x30000:     # RADIX_ROOT_PTE
  24                         # V = 1 L = 0 NLB = 0x400 NLS = 9
  25            0x8000000000040009,
  26            0x40000:     # RADIX_SECOND_LEVEL
  27                         # V = 1 L = 1 SW = 0 RPN = 0
  28                         # R = 1 C = 1 ATT = 0 EAA 0x7
  29            0xc000000000000187,
  30
  31            0x1000000:   # PROCESS_TABLE_3
  32                         # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
  33            0x40000000000300ad,
  34           }
  35
  36 prtbl = 0x1000000 # matches PROCESS_TABLE_3 above
  37
  38 class DecoderTestCase(FHDLTestCase):
  39
  40     def test_load(self):
  41         lst = [ "lwz 3, 0(1)"
  42                ]
  43         sprs = {'DSISR': SelectableInt(0, 64),
  44                 'DAR': SelectableInt(0, 64),
  45                 'PIDR': SelectableInt(0, 64),
  46                 'PRTBL': SelectableInt(prtbl, 64)
  47         }
  48
  49         initial_regs=[0] * 32
  50         initial_regs[1] = 0x1000
  51         initial_regs[2] = 0x1234
  52
  53         initial_mem = deepcopy(testmem)
  54         initial_mem[0x1000] = 0x1337 # data to be read
  55
  56         with Program(lst, bigendian=False) as program:
  57             sim = self.run_tst_program(program, initial_regs=initial_regs,
  58                                                 initial_mem=initial_mem,
  59                                                 initial_sprs=sprs)
  60             self.assertEqual(sim.gpr(3), SelectableInt(0x1337, 64))
  61
  62     def test_load_store(self):
  63         lst = ["addi 1, 0, 0x1000",
  64                "addi 2, 0, 0x1234",
  65                "stw 2, 0(1)",
  66                "lwz 3, 0(1)"
  67                ]
  68         # set up dummy minimal ISACaller
  69         sprs = {'DSISR': SelectableInt(0, 64),
  70                 'DAR': SelectableInt(0, 64),
  71                 'PIDR': SelectableInt(0, 64),
  72                 'PRTBL': SelectableInt(prtbl, 64)
  73         }
  74
  75         initial_regs=[0] * 32
  76         initial_regs[1] = 0x1000
  77         initial_regs[2] = 0x1234
  78         initial_mem = deepcopy(testmem)
  79
  80         with Program(lst, bigendian=False) as program:
  81             sim = self.run_tst_program(program, initial_regs=initial_regs,
  82                                                 initial_mem=initial_mem,
  83                                                 initial_sprs=sprs)
  84             self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
  85
  86     def run_tst_program(self, prog, initial_regs=None, initial_mem=None,
  87                                     initial_sprs=None):
  88         # DO NOT set complex arguments, it is a "singleton" pattern
  89         if initial_regs is None:
  90             initial_regs = [0] * 32
  91
  92         simulator = run_tst(prog, initial_regs, mmu=True, mem=initial_mem,
  93                     initial_sprs=initial_sprs)
  94         simulator.gpr.dump()
  95         return simulator
  96
  97
  98 if __name__ == "__main__":
  99     unittest.main()