src/soc/decoder/isa/test_caller_svp64_predication.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, SVP64State
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import Register, run_tst
  14 from soc.sv.trans.svp64 import SVP64Asm
  15 from soc.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def tst_sv_load_store(self):
  25         lst = SVP64Asm(["addi 1, 0, 0x0010",
  26                         "addi 2, 0, 0x0008",
  27                         "addi 5, 0, 0x1234",
  28                         "addi 6, 0, 0x1235",
  29                         "svstw 5.v, 0(1.v)",
  30                         "svlwz 9.v, 0(1.v)"])
  31         lst = list(lst)
  32
  33         # SVSTATE (in this case, VL=2)
  34         svstate = SVP64State()
  35         svstate.vl[0:7] = 2 # VL
  36         svstate.maxvl[0:7] = 2 # MAXVL
  37         print ("SVSTATE", bin(svstate.spr.asint()))
  38
  39         with Program(lst, bigendian=False) as program:
  40             sim = self.run_tst_program(program, svstate=svstate)
  41             print(sim.gpr(1))
  42             self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
  43             self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
  44
  45     def test_sv_add_intpred(self):
  46         # adds, integer predicated mask r3=0b10
  47         #       1 = 5 + 9   => not to be touched (skipped)
  48         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  49         isa = SVP64Asm(['svadd/m=r3 1.v, 5.v, 9.v'
  50                        ])
  51         lst = list(isa)
  52         print ("listing", lst)
  53
  54         # initial values in GPR regfile
  55         initial_regs = [0] * 32
  56         initial_regs[1] = 0xbeef   # not to be altered
  57         initial_regs[3] = 0b10   # predicate mask
  58         initial_regs[9] = 0x1234
  59         initial_regs[10] = 0x1111
  60         initial_regs[5] = 0x4321
  61         initial_regs[6] = 0x2223
  62         # SVSTATE (in this case, VL=2)
  63         svstate = SVP64State()
  64         svstate.vl[0:7] = 2 # VL
  65         svstate.maxvl[0:7] = 2 # MAXVL
  66         print ("SVSTATE", bin(svstate.spr.asint()))
  67         # copy before running
  68         expected_regs = deepcopy(initial_regs)
  69         expected_regs[1] = 0xbeef
  70         expected_regs[2] = 0x3334
  71
  72         with Program(lst, bigendian=False) as program:
  73             sim = self.run_tst_program(program, initial_regs, svstate)
  74             self._check_regs(sim, expected_regs)
  75
  76     def test_sv_add_cr_pred(self):
  77         # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
  78         #       1 = 5 + 9   => not to be touched (skipped)
  79         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  80         isa = SVP64Asm(['svadd/m=ne 1.v, 5.v, 9.v'
  81                        ])
  82         lst = list(isa)
  83         print ("listing", lst)
  84
  85         # initial values in GPR regfile
  86         initial_regs = [0] * 32
  87         initial_regs[1] = 0xbeef   # not to be altered
  88         initial_regs[9] = 0x1234
  89         initial_regs[10] = 0x1111
  90         initial_regs[5] = 0x4321
  91         initial_regs[6] = 0x2223
  92         # SVSTATE (in this case, VL=2)
  93         svstate = SVP64State()
  94         svstate.vl[0:7] = 2 # VL
  95         svstate.maxvl[0:7] = 2 # MAXVL
  96         print ("SVSTATE", bin(svstate.spr.asint()))
  97         # copy before running
  98         expected_regs = deepcopy(initial_regs)
  99         expected_regs[1] = 0xbeef
 100         expected_regs[2] = 0x3334
 101
 102         # set up CR predicate - CR4.eq=0 and CR5.eq=1
 103         cr = (0b0010) << ((7-4)*4) # CR5.eq (we hope)
 104
 105         with Program(lst, bigendian=False) as program:
 106             sim = self.run_tst_program(program, initial_regs, svstate,
 107                                        initial_cr=cr)
 108             self._check_regs(sim, expected_regs)
 109
 110     def tst_sv_add_2(self):
 111         # adds:
 112         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 113         #       r1 is scalar so ENDS EARLY
 114         isa = SVP64Asm(['svadd 1, 5.v, 9.v'
 115                        ])
 116         lst = list(isa)
 117         print ("listing", lst)
 118
 119         # initial values in GPR regfile
 120         initial_regs = [0] * 32
 121         initial_regs[9] = 0x1234
 122         initial_regs[10] = 0x1111
 123         initial_regs[5] = 0x4321
 124         initial_regs[6] = 0x2223
 125         # SVSTATE (in this case, VL=2)
 126         svstate = SVP64State()
 127         svstate.vl[0:7] = 2 # VL
 128         svstate.maxvl[0:7] = 2 # MAXVL
 129         print ("SVSTATE", bin(svstate.spr.asint()))
 130         # copy before running
 131         expected_regs = deepcopy(initial_regs)
 132         expected_regs[1] = 0x5555
 133
 134         with Program(lst, bigendian=False) as program:
 135             sim = self.run_tst_program(program, initial_regs, svstate)
 136             self._check_regs(sim, expected_regs)
 137
 138     def tst_sv_add_3(self):
 139         # adds:
 140         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 141         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
 142         isa = SVP64Asm(['svadd 1.v, 5, 9.v'
 143                        ])
 144         lst = list(isa)
 145         print ("listing", lst)
 146
 147         # initial values in GPR regfile
 148         initial_regs = [0] * 32
 149         initial_regs[9] = 0x1234
 150         initial_regs[10] = 0x1111
 151         initial_regs[5] = 0x4321
 152         initial_regs[6] = 0x2223
 153         # SVSTATE (in this case, VL=2)
 154         svstate = SVP64State()
 155         svstate.vl[0:7] = 2 # VL
 156         svstate.maxvl[0:7] = 2 # MAXVL
 157         print ("SVSTATE", bin(svstate.spr.asint()))
 158         # copy before running
 159         expected_regs = deepcopy(initial_regs)
 160         expected_regs[1] = 0x5555
 161         expected_regs[2] = 0x5432
 162
 163         with Program(lst, bigendian=False) as program:
 164             sim = self.run_tst_program(program, initial_regs, svstate)
 165             self._check_regs(sim, expected_regs)
 166
 167     def tst_sv_add_vl_0(self):
 168         # adds:
 169         #       none because VL is zer0
 170         isa = SVP64Asm(['svadd 1, 5.v, 9.v'
 171                        ])
 172         lst = list(isa)
 173         print ("listing", lst)
 174
 175         # initial values in GPR regfile
 176         initial_regs = [0] * 32
 177         initial_regs[9] = 0x1234
 178         initial_regs[10] = 0x1111
 179         initial_regs[5] = 0x4321
 180         initial_regs[6] = 0x2223
 181         # SVSTATE (in this case, VL=0)
 182         svstate = SVP64State()
 183         svstate.vl[0:7] = 0 # VL
 184         svstate.maxvl[0:7] = 0 # MAXVL
 185         print ("SVSTATE", bin(svstate.spr.asint()))
 186         # copy before running
 187         expected_regs = deepcopy(initial_regs)
 188
 189         with Program(lst, bigendian=False) as program:
 190             sim = self.run_tst_program(program, initial_regs, svstate)
 191             self._check_regs(sim, expected_regs)
 192
 193     def tst_sv_add_cr(self):
 194         # adds when Rc=1:                               TODO CRs higher up
 195         #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
 196         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
 197         isa = SVP64Asm(['svadd. 1.v, 5.v, 9.v'
 198                        ])
 199         lst = list(isa)
 200         print ("listing", lst)
 201
 202         # initial values in GPR regfile
 203         initial_regs = [0] * 32
 204         initial_regs[9] = 0xffffffffffffffff
 205         initial_regs[10] = 0x1111
 206         initial_regs[5] = 0x1
 207         initial_regs[6] = 0x2223
 208         # SVSTATE (in this case, VL=2)
 209         svstate = SVP64State()
 210         svstate.vl[0:7] = 2 # VL
 211         svstate.maxvl[0:7] = 2 # MAXVL
 212         print ("SVSTATE", bin(svstate.spr.asint()))
 213         # copy before running
 214         expected_regs = deepcopy(initial_regs)
 215         expected_regs[1] = 0
 216         expected_regs[2] = 0x3334
 217
 218         with Program(lst, bigendian=False) as program:
 219             sim = self.run_tst_program(program, initial_regs, svstate)
 220             # XXX TODO, these need to move to higher range (offset)
 221             cr0_idx = SVP64CROffs.CR0
 222             cr1_idx = SVP64CROffs.CR1
 223             CR0 = sim.crl[cr0_idx].get_range().value
 224             CR1 = sim.crl[cr1_idx].get_range().value
 225             print ("CR0", CR0)
 226             print ("CR1", CR1)
 227             self._check_regs(sim, expected_regs)
 228             self.assertEqual(CR0, SelectableInt(2, 4))
 229             self.assertEqual(CR1, SelectableInt(4, 4))
 230
 231     def run_tst_program(self, prog, initial_regs=None,
 232                               svstate=None,
 233                               initial_cr=0):
 234         if initial_regs is None:
 235             initial_regs = [0] * 32
 236         simulator = run_tst(prog, initial_regs, svstate=svstate,
 237                             initial_cr=initial_cr)
 238         simulator.gpr.dump()
 239         return simulator
 240
 241
 242 if __name__ == "__main__":
 243     unittest.main()