1 # SPDX-License: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020, Michael Nolan
5 from enum
import Enum
, unique
8 from os
.path
import dirname
, join
9 from collections
import namedtuple
13 filedir
= os
.path
.dirname(os
.path
.abspath(__file__
))
14 basedir
= dirname(dirname(dirname(filedir
)))
15 tabledir
= join(basedir
, 'libreriscv')
16 tabledir
= join(tabledir
, 'openpower')
17 return join(tabledir
, 'isatables')
19 def find_wiki_file(name
):
20 filedir
= os
.path
.dirname(os
.path
.abspath(__file__
))
21 basedir
= dirname(dirname(dirname(filedir
)))
22 tabledir
= join(basedir
, 'libreriscv')
23 tabledir
= join(tabledir
, 'openpower')
24 tabledir
= join(tabledir
, 'isatables')
26 return join(find_wiki_dir(), name
)
30 file_path
= find_wiki_file(name
)
31 with
open(file_path
, 'r') as csvfile
:
32 reader
= csv
.DictReader(csvfile
)
36 # names of the fields in the tables that don't correspond to an enum
37 single_bit_flags
= ['inv A', 'inv out',
38 'cry out', 'BR', 'sgn ext', 'rsrv', '32b',
39 'sgn', 'lk', 'sgl pipe']
41 # default values for fields in the table
42 default_values
= {'unit': "NONE", 'internal op': "OP_ILLEGAL",
43 'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
47 'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
50 def get_signal_name(name
):
53 return name
.lower().replace(' ', '_')
55 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
56 # is to process and guard the operation. they are roughly divided by having
57 # the same register input/output signature (X-Form, etc.)
72 SV
= 1 << 12 # Simple-V https://libre-soc.org/openpower/sv
107 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
121 # supported instructions: make sure to keep up-to-date with CSV files
122 # just like everything else
124 "NONE", "add", "addc", "addco", "adde", "addeo", "addi", "addic", "addic.",
125 "addis", "addme", "addmeo", "addo", "addze", "addzeo", "and", "andc",
126 "andi.", "andis.", "attn", "b", "bc", "bcctr", "bclr", "bctar",
127 "bpermd", "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
128 "cntlzd", "cntlzw", "cnttzd", "cnttzw", "crand", "crandc", "creqv",
129 "crnand", "crnor", "cror", "crorc", "crxor", "darn", "dcbf", "dcbst",
130 "dcbt", "dcbtst", "dcbz", "divd", "divde", "divdeo", "divdeu",
131 "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
132 "divweu", "divweuo", "divwo", "divwu", "divwuo", "eqv", "extsb",
133 "extsh", "extsw", "extswsli", "hrfid", "icbi", "icbt", "isel", "isync",
134 "lbarx", "lbz", "lbzu", "lbzux", "lbzx", "ld", "ldarx", "ldbrx",
135 "ldu", "ldux", "ldx", "lha", "lharx", "lhau", "lhaux", "lhax",
136 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", "lwa", "lwarx", "lwaux",
137 "lwax", "lwbrx", "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", "mcrf", "mcrxr",
138 "mcrxrx", "mfcr/mfocrf", "mfmsr", "mfspr", "modsd", "modsw", "modud",
139 "moduw", "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr", "mulhd", "mulhdu",
140 "mulhw", "mulhwu", "mulld", "mulldo", "mulli", "mullw", "mullwo",
141 "nand", "neg", "nego", "nop", "nor", "or", "orc", "ori", "oris",
142 "popcntb", "popcntd", "popcntw", "prtyd", "prtyw", "rfid", "rldcl",
143 "rldcr", "rldic", "rldicl", "rldicr", "rldimi", "rlwimi", "rlwinm",
145 "setvl", # https://libre-soc.org/openpower/sv/setvl
146 "sim_cfg", "slbia", "sld", "slw", "srad", "sradi", "sraw",
147 "srawi", "srd", "srw", "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
148 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx", "sth", "sthbrx", "sthcx",
149 "sthu", "sthux", "sthx", "stw", "stwbrx", "stwcx", "stwu", "stwux",
150 "stwx", "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
151 "subfme", "subfmeo", "subfo", "subfze", "subfzeo", "sync", "td",
152 "tdi", "tlbie", "tlbiel", "tw", "twi", "xor", "xori", "xoris",
155 # two-way lookup of instruction-to-index and vice-versa
158 for i
, insn
in enumerate(_insns
):
162 # Internal Operation numbering. Add new opcodes here (FPADD, FPMUL etc.)
165 OP_ILLEGAL
= 0 # important that this is zero (see power_decoder.py)
246 RS
= 4 # for some ALU/Logical operations
264 RS
= 13 # for shiftrot (M-Form)
271 RB
= 2 # for shiftrot (M-Form)
292 class LDSTMode(Enum
):
327 class CROutSel(Enum
):
336 # SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
337 # http://libre-riscv.org/openpower/isatables/sprs.csv
338 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
340 spr_csv
= get_csv("sprs.csv")
341 spr_info
= namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
345 info
= spr_info(SPR
=row
['SPR'], priv_mtspr
=row
['priv_mtspr'],
346 priv_mfspr
=row
['priv_mfspr'], length
=int(row
['len']),
348 spr_dict
[int(row
['Idx'])] = info
349 spr_byname
[row
['SPR']] = info
350 fields
= [(row
['SPR'], int(row
['Idx'])) for row
in spr_csv
]
351 SPR
= Enum('SPR', fields
)
362 if __name__
== '__main__':
363 # find out what the heck is in SPR enum :)
364 print("sprs", len(SPR
))
367 print(SPR
.__members
__['TAR'])
369 print(x
, x
.value
, str(x
), x
.name
)
371 print ("function", Function
.ALU
.name
)