1 from collections
import OrderedDict
2 from soc
.decoder
.power_fields
import DecodeFields
, BitRange
3 from nmigen
import Module
, Elaboratable
, Signal
, Cat
4 from nmigen
.cli
import rtlil
7 class SignalBitRange(BitRange
):
8 def __init__(self
, signal
):
9 BitRange
.__init
__(self
)
13 width
= self
.signal
.width
16 def __getitem__(self
, subs
):
17 # *sigh* field numberings are bit-inverted. PowerISA 3.0B section 1.3.2
18 if isinstance(subs
, slice):
20 start
, stop
, step
= subs
.start
, subs
.stop
, subs
.step
28 start
= len(self
) + start
+ 1
30 stop
= len(self
) + stop
+ 1
31 for t
in range(start
, stop
, step
):
32 t
= len(self
) - 1 - t
# invert field back
33 k
= OrderedDict
.__getitem
__(self
, t
)
34 res
.append(self
.signal
[self
._rev
(k
)]) # reverse-order here
38 subs
= len(self
) + subs
39 subs
= len(self
) - 1 - subs
# invert field back
40 k
= OrderedDict
.__getitem
__(self
, subs
)
41 return self
.signal
[self
._rev
(k
)] # reverse-order here
44 class SigDecode(Elaboratable
):
46 def __init__(self
, width
):
47 self
.opcode_in
= Signal(width
, reset_less
=False)
48 self
.df
= DecodeFields(SignalBitRange
, [self
.opcode_in
])
49 self
.df
.create_specs()
51 def elaborate(self
, platform
):
57 return [self
.opcode_in
]
60 def create_sigdecode():
65 if __name__
== '__main__':
66 sigdecode
= create_sigdecode()
67 vl
= rtlil
.convert(sigdecode
, ports
=sigdecode
.ports())
68 with
open("decoder.il", "w") as f
: