identify [0]*16 pattern and produce repeat-of-int
[soc.git] / src / soc / decoder / power_pseudo.py
1 # Based on GardenSnake - a parser generator demonstration program
2 # GardenSnake was released into the Public Domain by Andrew Dalke.
3
4 # Portions of this work are derived from Python's Grammar definition
5 # and may be covered under the Python copyright and license
6 #
7 # Andrew Dalke / Dalke Scientific Software, LLC
8 # 30 August 2006 / Cape Town, South Africa
9
10 # Modifications for inclusion in PLY distribution
11 import sys
12 from pprint import pprint
13 from copy import copy
14 from ply import lex, yacc
15 import astor
16 import ast
17
18 from soc.decoder.power_decoder import create_pdecode
19 from nmigen.back.pysim import Simulator, Delay
20 from nmigen import Module, Signal
21
22 from soc.decoder.pseudo.parser import GardenSnakeCompiler
23 from soc.decoder.selectable_int import SelectableInt, selectconcat
24
25 ####### Test code #######
26
27 bpermd = r"""
28 perm <- [0] * 8
29 if index < 64:
30 index <- (RS)[8*i:8*i+7]
31 RA <- [0]*56 || perm[0:7]
32 print (RA)
33 """
34
35 bpermd = r"""
36 if index < 64 then index <- 0
37 else index <- 5
38 do while index < 5
39 index <- 0
40 leave
41 for i = 0 to 7
42 index <- 0
43 """
44
45 _bpermd = r"""
46 for i = 0 to 7
47 index <- (RS)[8*i:8*i+7]
48 if index < 64 then
49 permi <- (RB)[index]
50 else
51 permi <- 0
52 RA <- [0]*56|| perm[0:7]
53 """
54
55 cnttzd = """
56 n <- 0
57 do while n < 64
58 print (n)
59 if (RS)[63-n] = 0b1 then
60 leave
61 n <- n + 1
62 RA <- EXTZ64(n)
63 print (RA)
64 """
65
66 cmpi = """
67 if a < EXTS(SI) then
68 c <- 0b100
69 else if a > EXTS(SI) then
70 c <- 0b010
71 """
72
73 cmpi = """
74 RA[0:1] <- 0b11
75 """
76
77 cmpi = """
78 in_range <- ((x | y) &
79 (a | b))
80 in_range <- (x + y) - (a + b)
81 """
82
83 cmpi = """
84 (RA)[0:1] <- 1
85 src1 <- EXTZ((RA)[56:63])
86 CR[4*BF+32] <- 0b0
87 in_range <- src21lo <= src1 & src1 <= src21hi
88 """
89
90 cmpeqb = """
91 src1 <- GPR[RA]
92 src1 <- src1[0:56]
93 """
94
95 addpcis = """
96 D <- d0||d1||d2
97 """
98
99 testmul = """
100 x <- [0] * 16
101 RT <- (RA) + EXTS(SI || [0]*16)
102 """
103
104 code = testmul
105 #code = testreg
106 #code = cnttzd
107 #code = cmpi
108 #code = cmpeqb
109 #code = addpcis
110 #code = bpermd
111
112
113 def tolist(num):
114 l = []
115 for i in range(64):
116 l.append(1 if (num & (1 << i)) else 0)
117 l.reverse()
118 return l
119
120
121 def get_reg_hex(reg):
122 return hex(reg.value)
123
124
125 class GPR(dict):
126 def __init__(self, sd, regfile):
127 dict.__init__(self)
128 self.sd = sd
129 self.regfile = regfile
130 for i in range(32):
131 self[i] = SelectableInt(0, 64)
132
133 def set_form(self, form):
134 self.form = form
135
136 def ___getitem__(self, attr):
137 print("GPR getitem", attr)
138 getform = self.sd.sigforms[self.form]
139 rnum = getattr(getform, attr)
140 print("GPR get", rnum, rnum, dir(rnum))
141 l = list(rnum)
142 print(l[0]._as_const())
143 # for x in rnum:
144 #print (x, x.value, dir(x))
145 #print (x.value, dir(x.value))
146 print(list(rnum))
147 return self.regfile[rnum]
148
149
150 def convert_to_python(pcode):
151
152 gsc = GardenSnakeCompiler()
153
154 tree = gsc.compile(pcode, mode="exec", filename="string")
155 tree = ast.fix_missing_locations(tree)
156 regsused = {'read_regs': gsc.parser.read_regs,
157 'write_regs': gsc.parser.write_regs,
158 'uninit_regs': gsc.parser.uninit_regs}
159 return astor.to_source(tree), regsused
160
161
162 def test():
163
164 gsc = GardenSnakeCompiler()
165
166 # XXX unused! see GPR instead
167 gsc.regfile = {}
168 for i in range(32):
169 gsc.regfile[i] = 0
170 gsc.gpr = GPR(gsc.parser.sd, gsc.regfile)
171
172 _compile = gsc.compile
173
174 tree = _compile(code, mode="single", filename="string")
175 tree = ast.fix_missing_locations(tree)
176 print(ast.dump(tree))
177
178 print("astor dump")
179 print(astor.dump_tree(tree))
180 print("to source")
181 source = astor.to_source(tree)
182 print(source)
183
184 # sys.exit(0)
185
186 # Set up the GardenSnake run-time environment
187 def print_(*args):
188 print("args", args)
189 print("-->", " ".join(map(str, args)))
190
191 from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,)
192
193 d = {}
194 d["print"] = print_
195 d["EXTS64"] = EXTS64
196 d["EXTZ64"] = EXTZ64
197 d["SelectableInt"] = SelectableInt
198 d["concat"] = selectconcat
199 d["GPR"] = gsc.gpr
200
201 form = 'X'
202 gsc.gpr.set_form(form)
203 getform = gsc.parser.sd.sigforms[form]._asdict()
204 #print ("getform", form)
205 # for k, f in getform.items():
206 #print (k, f)
207 #d[k] = getform[k]
208
209 compiled_code = compile(source, mode="exec", filename="<string>")
210
211 m = Module()
212 comb = m.d.comb
213 instruction = Signal(32)
214
215 m.submodules.decode = decode = gsc.parser.sd
216 comb += decode.raw_opcode_in.eq(instruction)
217 sim = Simulator(m)
218
219 instr = [0x11111117]
220
221 def process():
222 for ins in instr:
223 print("0x{:X}".format(ins & 0xffffffff))
224
225 # ask the decoder to decode this binary data (endian'd)
226 yield decode.bigendian.eq(0) # little / big?
227 yield instruction.eq(ins) # raw binary instr.
228 yield Delay(1e-6)
229
230 # uninitialised regs, drop them into dict for function
231 for rname in gsc.parser.uninit_regs:
232 d[rname] = SelectableInt(0, 64) # uninitialised (to zero)
233 print("uninitialised", rname, get_reg_hex(d[rname]))
234
235 # read regs, drop them into dict for function
236 for rname in gsc.parser.read_regs:
237 regidx = yield getattr(decode.sigforms['X'], rname)
238 d[rname] = gsc.gpr[regidx]
239 print("read reg", rname, regidx, get_reg_hex(d[rname]))
240
241 exec(compiled_code, d) # code gets executed here in dict "d"
242 print("Done")
243
244 print(d.keys()) # shows the variables that may have been created
245
246 print(decode.sigforms['X'])
247 x = yield decode.sigforms['X'].RS
248 ra = yield decode.sigforms['X'].RA
249 print("RA", ra, d['RA'])
250 print("RS", x)
251
252 for wname in gsc.parser.write_regs:
253 reg = getform[wname]
254 print("write regs", wname, d[wname], reg)
255 regidx = yield reg
256 gsc.gpr[regidx] = d[wname]
257
258 sim.add_process(process)
259 with sim.write_vcd("simulator.vcd", "simulator.gtkw",
260 traces=decode.ports()):
261 sim.run()
262
263 for i in range(len(gsc.gpr)):
264 print("regfile", i, get_reg_hex(gsc.gpr[i]))
265
266
267 if __name__ == '__main__':
268 test()