1 # Based on GardenSnake - a parser generator demonstration program
2 # GardenSnake was released into the Public Domain by Andrew Dalke.
4 # Portions of this work are derived from Python's Grammar definition
5 # and may be covered under the Python copyright and license
7 # Andrew Dalke / Dalke Scientific Software, LLC
8 # 30 August 2006 / Cape Town, South Africa
10 # Modifications for inclusion in PLY distribution
12 from pprint
import pprint
14 from ply
import lex
, yacc
18 from soc
.decoder
.power_decoder
import create_pdecode
19 from nmigen
.back
.pysim
import Simulator
, Delay
20 from nmigen
import Module
, Signal
22 from soc
.decoder
.pseudo
.parser
import GardenSnakeCompiler
23 from soc
.decoder
.selectable_int
import SelectableInt
, selectconcat
24 from soc
.decoder
.isa
.caller
import GPR
, Mem
27 ####### Test code #######
32 index <- (RS)[8*i:8*i+7]
33 RA <- [0]*56 || perm[0:7]
38 if index < 64 then index <- 0
49 index <- (RS)[8*i:8*i+7]
54 RA <- [0]*56|| perm[0:7]
61 if (RS)[63-n] = 0b1 then
71 else if a > EXTS(SI) then
80 in_range <- ((x | y) &
82 in_range <- (x + y) - (a + b)
87 src1 <- EXTZ((RA)[56:63])
89 in_range <- src21lo <= src1 & src1 <= src21hi
103 RT <- (RA) + EXTS(SI || [0]*16)
113 RT <- (load_data[56:63] || load_data[48:55]
114 || load_data[40:47] || load_data[32:39]
115 || load_data[24:31] || load_data[16:23]
116 || load_data[8:15] || load_data[0:7])
127 MEM(EA, 1) <- (RS)[56:63]
133 MEM(EA, 4) <- GPR(r)[32:63]
154 l
.append(1 if (num
& (1 << i
)) else 0)
159 def get_reg_hex(reg
):
160 return hex(reg
.value
)
162 def convert_to_python(pcode
):
164 gsc
= GardenSnakeCompiler()
166 tree
= gsc
.compile(pcode
, mode
="exec", filename
="string")
167 tree
= ast
.fix_missing_locations(tree
)
168 regsused
= {'read_regs': gsc
.parser
.read_regs
,
169 'write_regs': gsc
.parser
.write_regs
,
170 'uninit_regs': gsc
.parser
.uninit_regs
}
171 return astor
.to_source(tree
), regsused
176 gsc
= GardenSnakeCompiler()
181 gsc
.gpr
= GPR(gsc
.parser
.sd
, gsc
.regfile
)
184 _compile
= gsc
.compile
186 tree
= _compile(code
, mode
="single", filename
="string")
187 tree
= ast
.fix_missing_locations(tree
)
188 print(ast
.dump(tree
))
191 print(astor
.dump_tree(tree
))
193 source
= astor
.to_source(tree
)
198 # Set up the GardenSnake run-time environment
201 print("-->", " ".join(map(str, args
)))
203 from soc
.decoder
.helpers
import (EXTS64
, EXTZ64
, ROTL64
, ROTL32
, MASK
,)
209 d
["SelectableInt"] = SelectableInt
210 d
["concat"] = selectconcat
213 d
["memassign"] = gsc
.mem
.memassign
216 gsc
.gpr
.set_form(form
)
217 getform
= gsc
.parser
.sd
.sigforms
[form
]._asdict
()
218 #print ("getform", form)
219 # for k, f in getform.items():
223 compiled_code
= compile(source
, mode
="exec", filename
="<string>")
227 instruction
= Signal(32)
229 m
.submodules
.decode
= decode
= gsc
.parser
.sd
230 comb
+= decode
.raw_opcode_in
.eq(instruction
)
237 print("0x{:X}".format(ins
& 0xffffffff))
239 # ask the decoder to decode this binary data (endian'd)
240 yield decode
.bigendian
.eq(0) # little / big?
241 yield instruction
.eq(ins
) # raw binary instr.
244 # uninitialised regs, drop them into dict for function
245 for rname
in gsc
.parser
.uninit_regs
:
246 d
[rname
] = SelectableInt(0, 64) # uninitialised (to zero)
247 print("uninitialised", rname
, get_reg_hex(d
[rname
]))
249 # read regs, drop them into dict for function
250 for rname
in gsc
.parser
.read_regs
:
251 regidx
= yield getattr(decode
.sigforms
['X'], rname
)
252 d
[rname
] = gsc
.gpr
[regidx
] # contents of regfile
253 d
["_%s" % rname
] = regidx
# actual register value
254 print("read reg", rname
, regidx
, get_reg_hex(d
[rname
]))
256 exec(compiled_code
, d
) # code gets executed here in dict "d"
259 print(d
.keys()) # shows the variables that may have been created
261 print(decode
.sigforms
['X'])
262 x
= yield decode
.sigforms
['X'].RS
263 ra
= yield decode
.sigforms
['X'].RA
264 rb
= yield decode
.sigforms
['X'].RB
265 print("RA", ra
, d
['RA'])
266 print("RB", rb
, d
['RB'])
269 for wname
in gsc
.parser
.write_regs
:
272 print("write regs", regidx
, wname
, d
[wname
], reg
)
273 gsc
.gpr
[regidx
] = d
[wname
]
275 sim
.add_process(process
)
276 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
277 traces
=decode
.ports()):
280 for i
in range(len(gsc
.gpr
)):
281 print("regfile", i
, get_reg_hex(gsc
.gpr
[i
]))
283 for i
in range(0, len(gsc
.mem
.mem
), 16):
286 hexstr
.append("%02x" % gsc
.mem
.mem
[i
+j
])
287 hexstr
= ' '.join(hexstr
)
288 print ("mem %4x" % i
, hexstr
)
290 if __name__
== '__main__':