src/soc/decoder/test/test_power_decoder.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import os
   6 import unittest
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_enums import (Function, InternalOp,
   9                          In1Sel, In2Sel,In3Sel,
  10                          OutSel, RC, LdstLen, CryIn, single_bit_flags,
  11                          get_signal_name, get_csv)
  12
  13
  14 class DecoderTestCase(FHDLTestCase):
  15
  16     def run_tst(self, bitsel, csvname, minor=None, suffix=None, opint=True):
  17         m = Module()
  18         comb = m.d.comb
  19         opcode = Signal(32)
  20         function_unit = Signal(Function)
  21         internal_op = Signal(InternalOp)
  22         in1_sel = Signal(In1Sel)
  23         in2_sel = Signal(In2Sel)
  24         in3_sel = Signal(In3Sel)
  25         out_sel = Signal(OutSel)
  26         rc_sel = Signal(RC)
  27         ldst_len = Signal(LdstLen)
  28         cry_in = Signal(CryIn)
  29
  30         # opcodes = get_csv(csvname)
  31         m.submodules.dut = dut = create_pdecode()
  32         comb += [dut.opcode_in.eq(opcode),
  33                  function_unit.eq(dut.op.function_unit),
  34                  in1_sel.eq(dut.op.in1_sel),
  35                  in2_sel.eq(dut.op.in2_sel),
  36                  in3_sel.eq(dut.op.in3_sel),
  37                  out_sel.eq(dut.op.out_sel),
  38                  rc_sel.eq(dut.op.rc_sel),
  39                  ldst_len.eq(dut.op.ldst_len),
  40                  cry_in.eq(dut.op.cry_in),
  41                  internal_op.eq(dut.op.internal_op)]
  42
  43         sim = Simulator(m)
  44         opcodes = get_csv(csvname)
  45
  46         def process():
  47             for row in opcodes:
  48                 if not row['unit']:
  49                     continue
  50                 op = row['opcode']
  51                 if not opint: # HACK: convert 001---10 to 0b00100010
  52                     op = "0b" + op.replace('-', '0')
  53                 print ("opint", opint, row['opcode'], op)
  54                 print(row)
  55                 yield opcode.eq(0)
  56                 yield opcode[bitsel[0]:bitsel[1]].eq(int(op, 0))
  57                 if minor:
  58                     print(minor)
  59                     minorbits = minor[1]
  60                     yield opcode[minorbits[0]:minorbits[1]].eq(minor[0])
  61                 else:
  62                     # OR 0, 0, 0  ; 0x60000000 is decoded as a NOP
  63                     # If we're testing the OR instruction, make sure
  64                     # that the instruction is not 0x60000000
  65                     if int(op, 0) == 24:
  66                         yield opcode[24:25].eq(0b11)
  67
  68                 yield Delay(1e-6)
  69                 signals = [(function_unit, Function, 'unit'),
  70                            (internal_op, InternalOp, 'internal op'),
  71                            (in1_sel, In1Sel, 'in1'),
  72                            (in2_sel, In2Sel, 'in2'),
  73                            (in3_sel, In3Sel, 'in3'),
  74                            (out_sel, OutSel, 'out'),
  75                            (rc_sel, RC, 'rc'),
  76                            (cry_in, CryIn, 'cry in'),
  77                            (ldst_len, LdstLen, 'ldst len')]
  78                 for sig, enm, name in signals:
  79                     result = yield sig
  80                     expected = enm[row[name]]
  81                     msg = f"{sig.name} == {enm(result)}, expected: {expected}"
  82                     self.assertEqual(enm(result), expected, msg)
  83                 for bit in single_bit_flags:
  84                     sig = getattr(dut.op, get_signal_name(bit))
  85                     result = yield sig
  86                     expected = int(row[bit])
  87                     msg = f"{sig.name} == {result}, expected: {expected}"
  88                     self.assertEqual(expected, result, msg)
  89         sim.add_process(process)
  90         prefix = os.path.splitext(csvname)[0]
  91         with sim.write_vcd("%s.vcd" % prefix, "%s.gtkw" % prefix, traces=[
  92                 opcode, function_unit, internal_op,
  93                 in1_sel, in2_sel]):
  94             sim.run()
  95
  96     def generate_ilang(self):
  97         pdecode = create_pdecode()
  98         vl = rtlil.convert(pdecode, ports=pdecode.ports())
  99         with open("decoder.il", "w") as f:
 100             f.write(vl)
 101
 102     def test_major(self):
 103         self.run_tst((26, 32), "major.csv")
 104         self.generate_ilang()
 105
 106     def test_minor_19(self):
 107         self.run_tst((1, 11), "minor_19.csv", minor=(19, (26, 32)),
 108                      suffix=(0, 5))
 109
 110     # def test_minor_19_00000(self):
 111     #     self.run_tst((1, 11), "minor_19_00000.csv")
 112
 113     def test_minor_30(self):
 114         self.run_tst((1, 5), "minor_30.csv", minor=(30, (26, 32)))
 115
 116     def test_minor_31(self):
 117         self.run_tst((1, 11), "minor_31.csv", minor=(31, (26, 32)))
 118
 119     def test_minor_58(self):
 120         self.run_tst((0, 2), "minor_58.csv", minor=(58, (26, 32)))
 121
 122     def test_minor_62(self):
 123         self.run_tst((0, 2), "minor_62.csv", minor=(62, (26, 32)))
 124
 125
 126     # #def test_minor_31_prefix(self):
 127     # #    self.run_tst(10, "minor_31.csv", suffix=(5, 10))
 128
 129     # def test_extra(self):
 130     #     self.run_tst(32, "extra.csv", opint=False)
 131     #     self.generate_ilang(32, "extra.csv", opint=False)
 132
 133
 134 if __name__ == "__main__":
 135     unittest.main()