1 # TODO: replace with Memory at some point
2 from nmigen
import Elaboratable
, Signal
, Array
, Module
3 from nmutil
.util
import Display
5 class CacheRam(Elaboratable
):
7 def __init__(self
, ROW_BITS
=16, WIDTH
= 64, TRACE
=True, ADD_BUF
=False,
9 self
.ram_num
= ram_num
# for debug reporting
10 self
.ROW_BITS
= ROW_BITS
13 self
.ADD_BUF
= ADD_BUF
15 self
.rd_addr
= Signal(ROW_BITS
)
16 self
.rd_data_o
= Signal(WIDTH
)
17 self
.wr_sel
= Signal(WIDTH
//8)
18 self
.wr_addr
= Signal(ROW_BITS
)
19 self
.wr_data
= Signal(WIDTH
)
21 def elaborate(self
, platform
):
23 comb
, sync
= m
.d
.comb
, m
.d
.sync
25 ROW_BITS
= self
.ROW_BITS
28 ADD_BUF
= self
.ADD_BUF
31 ram
= Array(Signal(WIDTH
) for i
in range(SIZE
))
32 #attribute ram_style of ram : signal is "block";
34 rd_data0
= Signal(WIDTH
)
37 with m
.If(self
.wr_sel
.bool()):
38 sync
+= Display( "write ramno %d a: %%x "
39 "sel: %%x dat: %%x" % self
.ram_num
,
41 self
.wr_sel
, self
.wr_data
)
42 for i
in range(WIDTH
//8):
45 with m
.If(self
.wr_sel
[i
]):
46 sync
+= ram
[self
.wr_addr
][lbit
:mbit
].eq(self
.wr_data
[lbit
:mbit
])
47 with m
.If(self
.rd_en
):
48 sync
+= rd_data0
.eq(ram
[self
.rd_addr
])
50 sync
+= Display("read ramno %d a: %%x dat: %%x" % self
.ram_num
,
51 self
.rd_addr
, ram
[self
.rd_addr
])
56 sync
+= self
.rd_data_o
.eq(rd_data0
)
58 comb
+= self
.rd_data_o
.eq(rd_data0
)