src/soc/experiment/compalu_multi.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Mux, Elaboratable, Repl, Array
   4
   5 from nmutil.latch import SRLatch, latchregister
   6 from soc.decoder.power_decoder2 import Data
   7 from soc.decoder.power_enums import InternalOp
   8
   9 from alu_hier import CompALUOpSubset
  10
  11 """ Computation Unit (aka "ALU Manager").
  12
  13     This module runs a "revolving door" set of three latches, based on
  14     * Issue
  15     * Go_Read
  16     * Go_Write
  17     where one of them cannot be set on any given cycle.
  18     (Note however that opc_l has been inverted (and qn used), due to SRLatch
  19      default reset state being "0" rather than "1")
  20
  21     * When issue is first raised, a busy signal is sent out.
  22       The src1 and src2 registers and the operand can be latched in
  23       at this point
  24
  25     * Read request is set, which is acknowledged through the Scoreboard
  26       to the priority picker, which generates (one and only one) Go_Read
  27       at a time.  One of those will (eventually) be this Computation Unit.
  28
  29     * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
  30       src1/src2/operand in place), and the ALU is told to proceed.
  31
  32     * As this is currently a "demo" unit, a countdown timer is activated
  33       to simulate an ALU "pipeline", which activates "write request release",
  34       and the ALU's output is captured into a temporary register.
  35
  36     * Write request release will go through a similar process as Read request,
  37       resulting (eventually) in Go_Write being asserted.
  38
  39     * When Go_Write is asserted, two things happen: (1) the data in the temp
  40       register is placed combinatorially onto the output, and (2) the
  41       req_l latch is cleared, busy is dropped, and the Comp Unit is back
  42       through its revolving door to do another task.
  43 """
  44
  45
  46 class ComputationUnitNoDelay(Elaboratable):
  47     def __init__(self, rwid, alu, n_src=2, n_dst=1):
  48         self.n_src, self.n_dst = n_src, n_dst
  49         self.rwid = rwid
  50         self.alu = alu # actual ALU - set as a "submodule" of the CU
  51
  52         self.counter = Signal(4)
  53         src = []
  54         for i in range(n_src):
  55             j = i + 1 # name numbering to match src1/src2
  56             src.append(Signal(rwid, name="src%d_i" % j, reset_less=True))
  57
  58         dst = []
  59         for i in range(n_src):
  60             j = i + 1 # name numbering to match dest1/2...
  61             dst.append(Signal(rwid, name="dest%d_i" % j, reset_less=True))
  62
  63         self.go_rd_i = Signal(n_src, reset_less=True) # read in
  64         self.go_wr_i = Signal(n_dst, reset_less=True) # write in
  65         self.issue_i = Signal(reset_less=True) # fn issue in
  66         self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
  67         self.go_die_i = Signal() # go die (reset)
  68
  69         # operation / data input
  70         self.oper_i = CompALUOpSubset() # operand
  71         self.src_i = Array(src)
  72         self.src1_i = src[0] # oper1 in
  73         self.src2_i = src[1] # oper2 in
  74
  75         self.busy_o = Signal(reset_less=True) # fn busy out
  76         self.dest = Array(dst)
  77         self.data_o = dst[0] # Dest out
  78         self.rd_rel_o = Signal(n_src, reset_less=True) # release src1/src2
  79         self.req_rel_o = Signal(n_dst, reset_less=True) # release out (valid_o)
  80         self.done_o = self.req_rel_o # 'normalise' API
  81
  82     def elaborate(self, platform):
  83         m = Module()
  84         m.submodules.alu = self.alu
  85         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
  86         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
  87         m.submodules.req_l = req_l = SRLatch(False, self.n_dst, name="req")
  88         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
  89         m.submodules.rok_l = rok_l = SRLatch(sync=False, name="rdok")
  90
  91         # ALU only proceeds when all src are ready.  rd_rel_o is delayed
  92         # so combine it with go_rd_i.  if all bits are set we're good
  93         all_rd = Signal(reset_less=True)
  94         m.d.comb += all_rd.eq(self.busy_o & rok_l.q &
  95                     (((~self.rd_rel_o) | self.go_rd_i).all()))
  96
  97         # write_requests all done
  98         wr_any = Signal(reset_less=True)
  99         req_done = Signal(reset_less=True)
 100         m.d.comb += wr_any.eq(self.go_wr_i.bool())
 101         m.d.comb += req_done.eq(~(self.req_rel_o.bool()) & rst_l.q & wr_any)
 102
 103         # shadow/go_die
 104         reset = Signal(reset_less=True)
 105         rst_r = Signal(reset_less=True) # reset latch off
 106         reset_w = Signal(self.n_dst, reset_less=True)
 107         reset_r = Signal(self.n_src, reset_less=True)
 108         m.d.comb += reset.eq(req_done | self.go_die_i)
 109         m.d.comb += rst_r.eq(self.issue_i | self.go_die_i)
 110         m.d.comb += reset_w.eq(self.go_wr_i | Repl(self.go_die_i, self.n_dst))
 111         m.d.comb += reset_r.eq(self.go_rd_i | Repl(self.go_die_i, self.n_src))
 112
 113         # read-done,wr-proceed latch
 114         m.d.comb += rok_l.s.eq(self.issue_i)  # set up when issue starts
 115         m.d.comb += rok_l.r.eq(self.alu.p_ready_o) # off when ALU acknowledges
 116
 117         # wr-done, back-to-start latch
 118         m.d.comb += rst_l.s.eq(all_rd)     # set when read-phase is fully done
 119         m.d.comb += rst_l.r.eq(rst_r)        # *off* on issue
 120
 121         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
 122         m.d.sync += opc_l.s.eq(self.issue_i)       # set on issue
 123         m.d.sync += opc_l.r.eq(self.alu.n_valid_o) # reset on ALU finishes
 124
 125         # src operand latch (not using go_wr_i)
 126         m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src))
 127         m.d.sync += src_l.r.eq(reset_r)
 128
 129         # dest operand latch (not using issue_i)
 130         m.d.sync += req_l.s.eq(Repl(all_rd, self.n_dst))
 131         m.d.sync += req_l.r.eq(reset_w)
 132
 133         # create a latch/register for the operand
 134         oper_r = CompALUOpSubset()
 135         latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_r")
 136
 137         # and for each output from the ALU
 138         drl = []
 139         for i in range(self.n_dst):
 140             name = "data_r%d" % i
 141             data_r = Signal(self.rwid, name=name, reset_less=True)
 142             latchregister(m, self.alu.out[i], data_r, req_l.q[i], name)
 143             drl.append(data_r)
 144
 145         # pass the operation to the ALU
 146         m.d.comb += self.alu.op.eq(oper_r)
 147
 148         # create list of src/alu-src/src-latch.  override 2nd one below
 149         sl = []
 150         for i in range(self.n_src):
 151             sl.append([self.src_i[i], self.alu.i[i], src_l.q[i]])
 152
 153         # select immediate if opcode says so.  however also change the latch
 154         # to trigger *from* the opcode latch instead.
 155         op_is_imm = oper_r.imm_data.imm_ok
 156         src2_or_imm = Signal(self.rwid, reset_less=True)
 157         src_sel = Signal(reset_less=True)
 158         m.d.comb += src_sel.eq(Mux(op_is_imm, opc_l.q, src_l.q[1]))
 159         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm,
 160                                                   self.src2_i))
 161         # overwrite 2nd src-latch with immediate-muxed stuff
 162         sl[1][0] = src2_or_imm
 163         sl[1][2] = src_sel
 164
 165         # create a latch/register for src1/src2
 166         for i in range(self.n_src):
 167             src, alusrc, latch = sl[i]
 168             latchregister(m, src, alusrc, latch, name="src_r%d" % i)
 169
 170         # -----
 171         # outputs
 172         # -----
 173
 174         # all request signals gated by busy_o.  prevents picker problems
 175         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 176         bro = Repl(self.busy_o, self.n_src)
 177         m.d.comb += self.rd_rel_o.eq(src_l.q & bro) # src1/src2 req rel
 178
 179         # on a go_read, tell the ALU we're accepting data.
 180         # NOTE: this spells TROUBLE if the ALU isn't ready!
 181         # go_read is only valid for one clock!
 182         with m.If(all_rd):                           # src operands ready, GO!
 183             with m.If(~self.alu.p_ready_o):          # no ACK yet
 184                 m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
 185
 186         brd = Repl(self.busy_o & self.shadown_i, self.n_dst)
 187         # only proceed if ALU says its output is valid
 188         with m.If(self.alu.n_valid_o):
 189             # when ALU ready, write req release out. waits for shadow
 190             m.d.comb += self.req_rel_o.eq(req_l.q & brd)
 191             # when output latch is ready, and ALU says ready, accept ALU output
 192             with m.If(reset):
 193                 m.d.comb += self.alu.n_ready_i.eq(1) # tells ALU "thanks got it"
 194
 195         # output the data from the latch on go_write
 196         for i in range(self.n_dst):
 197             with m.If(self.go_wr_i[i]):
 198                 m.d.comb += self.dest[i].eq(drl[i])
 199
 200         return m
 201
 202     def __iter__(self):
 203         yield self.go_rd_i
 204         yield self.go_wr_i
 205         yield self.issue_i
 206         yield self.shadown_i
 207         yield self.go_die_i
 208         yield from self.oper_i.ports()
 209         yield self.src1_i
 210         yield self.src2_i
 211         yield self.busy_o
 212         yield self.rd_rel_o
 213         yield self.req_rel_o
 214         yield self.data_o
 215
 216     def ports(self):
 217         return list(self)
 218
 219
 220 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
 221     yield dut.issue_i.eq(0)
 222     yield
 223     yield dut.src_i[0].eq(a)
 224     yield dut.src_i[1].eq(b)
 225     yield dut.oper_i.insn_type.eq(op)
 226     yield dut.oper_i.invert_a.eq(inv_a)
 227     yield dut.oper_i.imm_data.imm.eq(imm)
 228     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 229     yield dut.issue_i.eq(1)
 230     yield
 231     yield dut.issue_i.eq(0)
 232     yield
 233     yield dut.go_rd_i.eq(0b10)
 234     yield
 235     yield dut.go_rd_i.eq(0b01)
 236     while True:
 237         yield
 238         rd_rel_o = yield dut.rd_rel_o
 239         print ("rd_rel", rd_rel_o)
 240         if rd_rel_o:
 241             break
 242     yield
 243     yield dut.go_rd_i.eq(0)
 244     req_rel_o = yield dut.req_rel_o
 245     result = yield dut.data_o
 246     print ("req_rel", req_rel_o, result)
 247     while True:
 248         req_rel_o = yield dut.req_rel_o
 249         result = yield dut.data_o
 250         print ("req_rel", req_rel_o, result)
 251         if req_rel_o:
 252             break
 253         yield
 254     yield dut.go_wr_i[0].eq(1)
 255     yield
 256     result = yield dut.data_o
 257     print ("result", result)
 258     yield dut.go_wr_i[0].eq(0)
 259     yield
 260     return result
 261
 262
 263 def scoreboard_sim(dut):
 264     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
 265                                     imm=8, imm_ok=1)
 266     assert result == 13
 267
 268     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
 269     assert result == 7
 270
 271     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
 272     assert result == 65532
 273
 274
 275 def test_scoreboard():
 276     from alu_hier import ALU
 277     from soc.decoder.power_decoder2 import Decode2ToExecute1Type
 278
 279     m = Module()
 280     alu = ALU(16)
 281     dut = ComputationUnitNoDelay(16, alu)
 282     m.submodules.cu = dut
 283     run_simulation(m, scoreboard_sim(dut), vcd_name='test_compalu.vcd')
 284
 285     vl = rtlil.convert(dut, ports=dut.ports())
 286     with open("test_compalu.il", "w") as f:
 287         f.write(vl)
 288
 289 if __name__ == '__main__':
 290     test_scoreboard()