convert CompALU to Record in/out
[soc.git] / src / soc / experiment / compalu_multi.py
1 from nmigen.compat.sim import run_simulation
2 from nmigen.cli import verilog, rtlil
3 from nmigen import Module, Signal, Mux, Elaboratable, Repl, Array, Record
4 from nmigen.hdl.rec import (DIR_FANIN, DIR_FANOUT)
5
6 from nmutil.latch import SRLatch, latchregister
7 from soc.decoder.power_decoder2 import Data
8 from soc.decoder.power_enums import InternalOp
9
10 from alu_hier import CompALUOpSubset
11
12 """ Computation Unit (aka "ALU Manager").
13
14 This module runs a "revolving door" set of three latches, based on
15 * Issue
16 * Go_Read
17 * Go_Write
18 where one of them cannot be set on any given cycle.
19 (Note however that opc_l has been inverted (and qn used), due to SRLatch
20 default reset state being "0" rather than "1")
21
22 * When issue is first raised, a busy signal is sent out.
23 The src1 and src2 registers and the operand can be latched in
24 at this point
25
26 * Read request is set, which is acknowledged through the Scoreboard
27 to the priority picker, which generates (one and only one) Go_Read
28 at a time. One of those will (eventually) be this Computation Unit.
29
30 * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
31 src1/src2/operand in place), and the ALU is told to proceed.
32
33 * As this is currently a "demo" unit, a countdown timer is activated
34 to simulate an ALU "pipeline", which activates "write request release",
35 and the ALU's output is captured into a temporary register.
36
37 * Write request release will go through a similar process as Read request,
38 resulting (eventually) in Go_Write being asserted.
39
40 * When Go_Write is asserted, two things happen: (1) the data in the temp
41 register is placed combinatorially onto the output, and (2) the
42 req_l latch is cleared, busy is dropped, and the Comp Unit is back
43 through its revolving door to do another task.
44 """
45
46 def go_record(n, name):
47 r = Record([('go', n, DIR_FANIN),
48 ('rel', n, DIR_FANOUT)], name=name)
49 r.go.reset_less = True
50 r.rel.reset_less = True
51 return r
52
53
54 class ComputationUnitNoDelay(Elaboratable):
55 def __init__(self, rwid, alu, n_src=2, n_dst=1):
56 self.n_src, self.n_dst = n_src, n_dst
57 self.rwid = rwid
58 self.alu = alu # actual ALU - set as a "submodule" of the CU
59
60 self.counter = Signal(4)
61 src = []
62 for i in range(n_src):
63 j = i + 1 # name numbering to match src1/src2
64 src.append(Signal(rwid, name="src%d_i" % j, reset_less=True))
65
66 dst = []
67 for i in range(n_dst):
68 j = i + 1 # name numbering to match dest1/2...
69 dst.append(Signal(rwid, name="dest%d_i" % j, reset_less=True))
70
71 self.rd = go_record(n_src, name="rd") # read in, req out
72 self.wr = go_record(n_dst, name="wr") # write in, req out
73 self.issue_i = Signal(reset_less=True) # fn issue in
74 self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
75 self.go_die_i = Signal() # go die (reset)
76
77 # operation / data input
78 self.oper_i = CompALUOpSubset() # operand
79 self.src_i = Array(src)
80 self.src1_i = src[0] # oper1 in
81 self.src2_i = src[1] # oper2 in
82
83 self.busy_o = Signal(reset_less=True) # fn busy out
84 self.dest = Array(dst)
85 self.data_o = dst[0] # Dest out
86 self.done_o = Signal(reset_less=True)
87
88 def elaborate(self, platform):
89 m = Module()
90 m.submodules.alu = self.alu
91 m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
92 m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
93 m.submodules.req_l = req_l = SRLatch(False, self.n_dst, name="req")
94 m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
95 m.submodules.rok_l = rok_l = SRLatch(sync=False, name="rdok")
96
97 # ALU only proceeds when all src are ready. rd_rel_o is delayed
98 # so combine it with go_rd_i. if all bits are set we're good
99 all_rd = Signal(reset_less=True)
100 m.d.comb += all_rd.eq(self.busy_o & rok_l.q &
101 (((~self.rd.rel) | self.rd.go).all()))
102
103 # write_requests all done
104 wr_any = Signal(reset_less=True)
105 req_done = Signal(reset_less=True)
106 m.d.comb += self.done_o.eq(self.busy_o & ~(self.wr.rel.bool()))
107 m.d.comb += wr_any.eq(self.wr.go.bool())
108 m.d.comb += req_done.eq(self.done_o & rst_l.q & wr_any)
109
110 # shadow/go_die
111 reset = Signal(reset_less=True)
112 rst_r = Signal(reset_less=True) # reset latch off
113 reset_w = Signal(self.n_dst, reset_less=True)
114 reset_r = Signal(self.n_src, reset_less=True)
115 m.d.comb += reset.eq(req_done | self.go_die_i)
116 m.d.comb += rst_r.eq(self.issue_i | self.go_die_i)
117 m.d.comb += reset_w.eq(self.wr.go | Repl(self.go_die_i, self.n_dst))
118 m.d.comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
119
120 # read-done,wr-proceed latch
121 m.d.comb += rok_l.s.eq(self.issue_i) # set up when issue starts
122 m.d.comb += rok_l.r.eq(self.alu.p_ready_o) # off when ALU acknowledges
123
124 # wr-done, back-to-start latch
125 m.d.comb += rst_l.s.eq(all_rd) # set when read-phase is fully done
126 m.d.comb += rst_l.r.eq(rst_r) # *off* on issue
127
128 # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
129 m.d.sync += opc_l.s.eq(self.issue_i) # set on issue
130 m.d.sync += opc_l.r.eq(self.alu.n_valid_o) # reset on ALU finishes
131
132 # src operand latch (not using go_wr_i)
133 m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src))
134 m.d.sync += src_l.r.eq(reset_r)
135
136 # dest operand latch (not using issue_i)
137 m.d.sync += req_l.s.eq(Repl(all_rd, self.n_dst))
138 m.d.sync += req_l.r.eq(reset_w)
139
140 # create a latch/register for the operand
141 oper_r = CompALUOpSubset()
142 latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_r")
143
144 # and for each output from the ALU
145 drl = []
146 for i in range(self.n_dst):
147 name = "data_r%d" % i
148 data_r = Signal(self.rwid, name=name, reset_less=True)
149 latchregister(m, self.alu.out[i], data_r, req_l.q[i], name)
150 drl.append(data_r)
151
152 # pass the operation to the ALU
153 m.d.comb += self.alu.op.eq(oper_r)
154
155 # create list of src/alu-src/src-latch. override 2nd one below
156 sl = []
157 for i in range(self.n_src):
158 sl.append([self.src_i[i], self.alu.i[i], src_l.q[i]])
159
160 # select immediate if opcode says so. however also change the latch
161 # to trigger *from* the opcode latch instead.
162 op_is_imm = oper_r.imm_data.imm_ok
163 src2_or_imm = Signal(self.rwid, reset_less=True)
164 src_sel = Signal(reset_less=True)
165 m.d.comb += src_sel.eq(Mux(op_is_imm, opc_l.q, src_l.q[1]))
166 m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm,
167 self.src2_i))
168 # overwrite 2nd src-latch with immediate-muxed stuff
169 sl[1][0] = src2_or_imm
170 sl[1][2] = src_sel
171
172 # create a latch/register for src1/src2
173 for i in range(self.n_src):
174 src, alusrc, latch = sl[i]
175 latchregister(m, src, alusrc, latch, name="src_r%d" % i)
176
177 # -----
178 # outputs
179 # -----
180
181 # all request signals gated by busy_o. prevents picker problems
182 m.d.comb += self.busy_o.eq(opc_l.q) # busy out
183 bro = Repl(self.busy_o, self.n_src)
184 m.d.comb += self.rd.rel.eq(src_l.q & bro) # src1/src2 req rel
185
186 # on a go_read, tell the ALU we're accepting data.
187 # NOTE: this spells TROUBLE if the ALU isn't ready!
188 # go_read is only valid for one clock!
189 with m.If(all_rd): # src operands ready, GO!
190 with m.If(~self.alu.p_ready_o): # no ACK yet
191 m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
192
193 brd = Repl(self.busy_o & self.shadown_i, self.n_dst)
194 # only proceed if ALU says its output is valid
195 with m.If(self.alu.n_valid_o):
196 # when ALU ready, write req release out. waits for shadow
197 m.d.comb += self.wr.rel.eq(req_l.q & brd)
198 # when output latch is ready, and ALU says ready, accept ALU output
199 with m.If(reset):
200 m.d.comb += self.alu.n_ready_i.eq(1) # tells ALU "thanks got it"
201
202 # output the data from the latch on go_write
203 for i in range(self.n_dst):
204 with m.If(self.wr.go[i]):
205 m.d.comb += self.dest[i].eq(drl[i])
206
207 return m
208
209 def __iter__(self):
210 yield self.rd.go
211 yield self.wr.go
212 yield self.issue_i
213 yield self.shadown_i
214 yield self.go_die_i
215 yield from self.oper_i.ports()
216 yield self.src1_i
217 yield self.src2_i
218 yield self.busy_o
219 yield self.rd.rel
220 yield self.wr.rel
221 yield self.data_o
222
223 def ports(self):
224 return list(self)
225
226
227 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
228 yield dut.issue_i.eq(0)
229 yield
230 yield dut.src_i[0].eq(a)
231 yield dut.src_i[1].eq(b)
232 yield dut.oper_i.insn_type.eq(op)
233 yield dut.oper_i.invert_a.eq(inv_a)
234 yield dut.oper_i.imm_data.imm.eq(imm)
235 yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
236 yield dut.issue_i.eq(1)
237 yield
238 yield dut.issue_i.eq(0)
239 yield
240 yield dut.rd.go.eq(0b11)
241 while True:
242 yield
243 rd_rel_o = yield dut.rd.rel
244 print ("rd_rel", rd_rel_o)
245 if rd_rel_o:
246 break
247 yield
248 yield dut.rd.go.eq(0)
249 req_rel_o = yield dut.wr.rel
250 result = yield dut.data_o
251 print ("req_rel", req_rel_o, result)
252 while True:
253 req_rel_o = yield dut.wr.rel
254 result = yield dut.data_o
255 print ("req_rel", req_rel_o, result)
256 if req_rel_o:
257 break
258 yield
259 yield dut.wr.go[0].eq(1)
260 yield
261 result = yield dut.data_o
262 print ("result", result)
263 yield dut.wr.go[0].eq(0)
264 yield
265 return result
266
267
268 def scoreboard_sim(dut):
269 result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
270 imm=8, imm_ok=1)
271 assert result == 13
272
273 result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
274 assert result == 7
275
276 result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
277 assert result == 65532
278
279
280 def test_scoreboard():
281 from alu_hier import ALU
282 from soc.decoder.power_decoder2 import Decode2ToExecute1Type
283
284 m = Module()
285 alu = ALU(16)
286 dut = ComputationUnitNoDelay(16, alu)
287 m.submodules.cu = dut
288
289 vl = rtlil.convert(dut, ports=dut.ports())
290 with open("test_compalu.il", "w") as f:
291 f.write(vl)
292
293 run_simulation(m, scoreboard_sim(dut), vcd_name='test_compalu.vcd')
294
295 if __name__ == '__main__':
296 test_scoreboard()