src/soc/experiment/compalu_multi.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Mux, Elaboratable, Repl, Array
   4
   5 from nmutil.latch import SRLatch, latchregister
   6 from soc.decoder.power_decoder2 import Data
   7 from soc.decoder.power_enums import InternalOp
   8
   9 from alu_hier import CompALUOpSubset
  10
  11 """ Computation Unit (aka "ALU Manager").
  12
  13     This module runs a "revolving door" set of three latches, based on
  14     * Issue
  15     * Go_Read
  16     * Go_Write
  17     where one of them cannot be set on any given cycle.
  18     (Note however that opc_l has been inverted (and qn used), due to SRLatch
  19      default reset state being "0" rather than "1")
  20
  21     * When issue is first raised, a busy signal is sent out.
  22       The src1 and src2 registers and the operand can be latched in
  23       at this point
  24
  25     * Read request is set, which is acknowledged through the Scoreboard
  26       to the priority picker, which generates (one and only one) Go_Read
  27       at a time.  One of those will (eventually) be this Computation Unit.
  28
  29     * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
  30       src1/src2/operand in place), and the ALU is told to proceed.
  31
  32     * As this is currently a "demo" unit, a countdown timer is activated
  33       to simulate an ALU "pipeline", which activates "write request release",
  34       and the ALU's output is captured into a temporary register.
  35
  36     * Write request release will go through a similar process as Read request,
  37       resulting (eventually) in Go_Write being asserted.
  38
  39     * When Go_Write is asserted, two things happen: (1) the data in the temp
  40       register is placed combinatorially onto the output, and (2) the
  41       req_l latch is cleared, busy is dropped, and the Comp Unit is back
  42       through its revolving door to do another task.
  43 """
  44
  45
  46 class ComputationUnitNoDelay(Elaboratable):
  47     def __init__(self, rwid, alu, n_src=2, n_dst=1):
  48         self.n_src, self.n_dst = n_src, n_dst
  49         self.rwid = rwid
  50         self.alu = alu # actual ALU - set as a "submodule" of the CU
  51
  52         self.counter = Signal(4)
  53         src = []
  54         for i in range(n_src):
  55             j = i + 1 # name numbering to match src1/src2
  56             src.append(Signal(rwid, name="src%d_i" % j, reset_less=True))
  57
  58         dst = []
  59         for i in range(n_src):
  60             j = i + 1 # name numbering to match dest1/2...
  61             dst.append(Signal(rwid, name="dest%d_i" % j, reset_less=True))
  62
  63         self.go_rd_i = Signal(n_src, name="gord_i", reset_less=True) # read in
  64         self.go_wr_i = Signal(n_dst, name="gowr_i", reset_less=True) # write in
  65         self.issue_i = Signal(reset_less=True) # fn issue in
  66         self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
  67         self.go_die_i = Signal() # go die (reset)
  68
  69         # operation / data input
  70         self.oper_i = CompALUOpSubset() # operand
  71         self.src_i = Array(src)
  72         self.src1_i = src[0] # oper1 in
  73         self.src2_i = src[1] # oper2 in
  74
  75         self.busy_o = Signal(reset_less=True) # fn busy out
  76         self.dest = Array(dst)
  77         self.data_o = dst[0] # Dest out
  78         self.rd_rel_o = Signal(n_src, reset_less=True) # release src1/src2
  79         self.req_rel_o = Signal(n_dst, reset_less=True) # release out (valid_o)
  80         self.done_o = self.req_rel_o # 'normalise' API
  81
  82     def elaborate(self, platform):
  83         m = Module()
  84         m.submodules.alu = self.alu
  85         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
  86         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
  87         m.submodules.req_l = req_l = SRLatch(False, self.n_dst, name="req")
  88         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
  89         m.submodules.rok_l = rok_l = SRLatch(sync=False, name="rdok")
  90
  91         # ALU only proceeds when all src are ready.
  92         all_rd = Signal(reset_less=True)
  93         m.d.comb += all_rd.eq(self.busy_o & rok_l.q & ~(self.rd_rel_o.bool()))
  94
  95         # write_requests all done
  96         wr_any = Signal(reset_less=True)
  97         req_done = Signal(reset_less=True)
  98         m.d.comb += wr_any.eq(self.go_wr_i.bool())
  99         m.d.comb += req_done.eq(~(self.req_rel_o.bool()) & rst_l.q & wr_any)
 100
 101         # shadow/go_die
 102         reset = Signal(reset_less=True)
 103         rst_r = Signal(reset_less=True) # reset latch off
 104         reset_w = Signal(self.n_dst, reset_less=True)
 105         reset_r = Signal(self.n_src, reset_less=True)
 106         m.d.comb += reset.eq(req_done | self.go_die_i)
 107         m.d.comb += rst_r.eq(self.issue_i | self.go_die_i)
 108         m.d.comb += reset_w.eq(self.go_wr_i | Repl(self.go_die_i, self.n_dst))
 109         m.d.comb += reset_r.eq(self.go_rd_i | Repl(self.go_die_i, self.n_src))
 110
 111         # read-done,wr-proceed latch
 112         m.d.comb += rok_l.s.eq(self.issue_i)  # set up when issue starts
 113         m.d.comb += rok_l.r.eq(self.alu.p_ready_o) # off when ALU acknowledges
 114
 115         # wr-done, back-to-start latch
 116         m.d.comb += rst_l.s.eq(all_rd)     # set when read-phase is fully done
 117         m.d.comb += rst_l.r.eq(rst_r)        # *off* on issue
 118
 119         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
 120         m.d.sync += opc_l.s.eq(self.issue_i)       # set on issue
 121         m.d.sync += opc_l.r.eq(self.alu.n_valid_o) # reset on ALU finishes
 122
 123         # src operand latch (not using go_wr_i)
 124         m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src))
 125         m.d.sync += src_l.r.eq(reset_r)
 126
 127         # dest operand latch (not using issue_i)
 128         m.d.sync += req_l.s.eq(Repl(all_rd, self.n_dst))
 129         m.d.sync += req_l.r.eq(reset_w)
 130
 131         # create a latch/register for the operand
 132         oper_r = CompALUOpSubset()
 133         latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_r")
 134
 135         # and for each output from the ALU
 136         drl = []
 137         for i in range(self.n_dst):
 138             name = "data_r%d" % i
 139             data_r = Signal(self.rwid, name=name, reset_less=True)
 140             latchregister(m, self.alu.out[i], data_r, req_l.q[i], name)
 141             drl.append(data_r)
 142
 143         # pass the operation to the ALU
 144         m.d.comb += self.alu.op.eq(oper_r)
 145
 146         # create list of src/alu-src/src-latch.  override 2nd one below
 147         sl = []
 148         for i in range(self.n_src):
 149             sl.append([self.src_i[i], self.alu.i[i], src_l.q[i]])
 150
 151         # select immediate if opcode says so.  however also change the latch
 152         # to trigger *from* the opcode latch instead.
 153         op_is_imm = oper_r.imm_data.imm_ok
 154         src2_or_imm = Signal(self.rwid, reset_less=True)
 155         src_sel = Signal(reset_less=True)
 156         m.d.comb += src_sel.eq(Mux(op_is_imm, opc_l.q, src_l.q[1]))
 157         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm,
 158                                                   self.src2_i))
 159         # overwrite 2nd src-latch with immediate-muxed stuff
 160         sl[1][0] = src2_or_imm
 161         sl[1][2] = src_sel
 162
 163         # create a latch/register for src1/src2
 164         for i in range(self.n_src):
 165             src, alusrc, latch = sl[i]
 166             latchregister(m, src, alusrc, latch, name="src_r%d" % i)
 167
 168         # -----
 169         # outputs
 170         # -----
 171
 172         # all request signals gated by busy_o.  prevents picker problems
 173         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 174         bro = Repl(self.busy_o, self.n_src)
 175         m.d.comb += self.rd_rel_o.eq(src_l.q & bro) # src1/src2 req rel
 176
 177         # on a go_read, tell the ALU we're accepting data.
 178         # NOTE: this spells TROUBLE if the ALU isn't ready!
 179         # go_read is only valid for one clock!
 180         with m.If(all_rd):                           # src operands ready, GO!
 181             with m.If(~self.alu.p_ready_o):          # no ACK yet
 182                 m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
 183
 184         brd = Repl(self.busy_o & self.shadown_i, self.n_dst)
 185         # only proceed if ALU says its output is valid
 186         with m.If(self.alu.n_valid_o):
 187             # when ALU ready, write req release out. waits for shadow
 188             m.d.comb += self.req_rel_o.eq(req_l.q & brd)
 189             # when output latch is ready, and ALU says ready, accept ALU output
 190             with m.If(reset):
 191                 m.d.comb += self.alu.n_ready_i.eq(1) # tells ALU "thanks got it"
 192
 193         # output the data from the latch on go_write
 194         for i in range(self.n_dst):
 195             with m.If(self.go_wr_i[i]):
 196                 m.d.comb += self.dest[i].eq(drl[i])
 197
 198         return m
 199
 200     def __iter__(self):
 201         yield self.go_rd_i
 202         yield self.go_wr_i
 203         yield self.issue_i
 204         yield self.shadown_i
 205         yield self.go_die_i
 206         yield from self.oper_i.ports()
 207         yield self.src1_i
 208         yield self.src2_i
 209         yield self.busy_o
 210         yield self.rd_rel_o
 211         yield self.req_rel_o
 212         yield self.data_o
 213
 214     def ports(self):
 215         return list(self)
 216
 217
 218 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
 219     yield dut.issue_i.eq(0)
 220     yield
 221     yield dut.src_i[0].eq(a)
 222     yield dut.src_i[1].eq(b)
 223     yield dut.oper_i.insn_type.eq(op)
 224     yield dut.oper_i.invert_a.eq(inv_a)
 225     yield dut.oper_i.imm_data.imm.eq(imm)
 226     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 227     yield dut.issue_i.eq(1)
 228     yield
 229     yield dut.issue_i.eq(0)
 230     yield
 231     yield dut.go_rd_i.eq(0b11)
 232     while True:
 233         yield
 234         rd_rel_o = yield dut.rd_rel_o
 235         print ("rd_rel", rd_rel_o)
 236         if rd_rel_o:
 237             break
 238     yield
 239     yield dut.go_rd_i.eq(0)
 240     req_rel_o = yield dut.req_rel_o
 241     result = yield dut.data_o
 242     print ("req_rel", req_rel_o, result)
 243     while True:
 244         req_rel_o = yield dut.req_rel_o
 245         result = yield dut.data_o
 246         print ("req_rel", req_rel_o, result)
 247         if req_rel_o:
 248             break
 249         yield
 250     yield dut.go_wr_i[0].eq(1)
 251     yield
 252     result = yield dut.data_o
 253     print ("result", result)
 254     yield dut.go_wr_i[0].eq(0)
 255     yield
 256     return result
 257
 258
 259 def scoreboard_sim(dut):
 260     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
 261                                     imm=8, imm_ok=1)
 262     assert result == 13
 263
 264     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
 265     assert result == 7
 266
 267     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
 268     assert result == 65532
 269
 270
 271 def test_scoreboard():
 272     from alu_hier import ALU
 273     from soc.decoder.power_decoder2 import Decode2ToExecute1Type
 274
 275     m = Module()
 276     alu = ALU(16)
 277     dut = ComputationUnitNoDelay(16, alu)
 278     m.submodules.cu = dut
 279     vl = rtlil.convert(dut, ports=dut.ports())
 280     with open("test_compalu.il", "w") as f:
 281         f.write(vl)
 282
 283     run_simulation(m, scoreboard_sim(dut), vcd_name='test_compalu.vcd')
 284
 285 if __name__ == '__main__':
 286     test_scoreboard()