1 """Computation Unit (aka "ALU Manager").
3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
4 monitored. At no time may the ALU proceed without this module notifying
5 the Dependency Matrices. At no time is a result production "abandoned".
6 This module blocks (indicates busy) starting from when it first receives
7 an opcode until it receives notification that
8 its result(s) have been successfully stored in the regfile(s)
10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
13 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Repl
, Cat
, Const
14 from nmigen
.hdl
.rec
import (Record
, DIR_FANIN
, DIR_FANOUT
)
16 from nmutil
.latch
import SRLatch
, latchregister
17 from nmutil
.iocontrol
import RecordObject
19 from soc
.fu
.regspec
import RegSpec
, RegSpecALUAPI
23 """find_ok helper function - finds field ending in "_ok"
25 for field_name
in fields
:
26 if field_name
.endswith("_ok"):
31 def go_record(n
, name
):
32 r
= Record([('go_i', n
, DIR_FANIN
),
33 ('rel_o', n
, DIR_FANOUT
)], name
=name
)
34 r
.go_i
.reset_less
= True
35 r
.rel_o
.reset_less
= True
39 # see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
41 class CompUnitRecord(RegSpec
, RecordObject
):
44 base class for Computation Units, to provide a uniform API
45 and allow "record.connect" etc. to be used, particularly when
46 it comes to connecting multiple Computation Units up as a block
49 LDSTCompUnitRecord should derive from this class and add the
50 additional signals it requires
52 :subkls: the class (not an instance) needed to construct the opcode
53 :rwid: either an integer (specifies width of all regs) or a "regspec"
55 see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
58 def __init__(self
, subkls
, rwid
, n_src
=None, n_dst
=None, name
=None):
59 RegSpec
.__init
__(self
, rwid
, n_src
, n_dst
)
61 RecordObject
.__init
__(self
)
63 n_src
, n_dst
= self
._n
_src
, self
._n
_dst
65 # create source operands
67 for i
in range(n_src
):
68 j
= i
+ 1 # name numbering to match src1/src2
70 rw
= self
._get
_srcwid
(i
)
71 sreg
= Signal(rw
, name
=sname
, reset_less
=True)
72 setattr(self
, sname
, sreg
)
76 # create dest operands
78 for i
in range(n_dst
):
79 j
= i
+ 1 # name numbering to match dest1/2...
80 dname
= "dest%d_o" % j
81 rw
= self
._get
_dstwid
(i
)
82 # dreg = Data(rw, name=name) XXX ??? output needs to be a Data type?
83 dreg
= Signal(rw
, name
=dname
, reset_less
=True)
84 setattr(self
, dname
, dreg
)
88 # operation / data input
89 self
.oper_i
= subkls(name
="oper_i_%s" % name
) # operand
91 # create read/write and other scoreboard signalling
92 self
.rd
= go_record(n_src
, name
="cu_rd") # read in, req out
93 self
.wr
= go_record(n_dst
, name
="cu_wr") # write in, req out
95 self
.rdmaskn
= Signal(n_src
, name
="cu_rdmaskn_i", reset_less
=True)
96 self
.wrmask
= Signal(n_dst
, name
="cu_wrmask_o", reset_less
=True)
99 self
.issue_i
= Signal(name
="cu_issue_i", reset_less
=True)
100 # shadow function, defaults to ON
101 self
.shadown_i
= Signal(name
="cu_shadown_i", reset
=1)
103 self
.go_die_i
= Signal(name
="cu_go_die_i")
106 self
.busy_o
= Signal(name
="cu_busy_o", reset_less
=True) # fn busy out
107 self
.done_o
= Signal(name
="cu_done_o", reset_less
=True)
110 class MultiCompUnit(RegSpecALUAPI
, Elaboratable
):
111 def __init__(self
, rwid
, alu
, opsubsetkls
, n_src
=2, n_dst
=1, name
=None):
114 * :rwid: width of register latches (TODO: allocate per regspec)
115 * :alu: ALU (pipeline, FSM) - must conform to nmutil Pipe API
116 * :opsubsetkls: subset of Decode2ExecuteType
117 * :n_src: number of src operands
118 * :n_dst: number of destination operands
120 RegSpecALUAPI
.__init
__(self
, rwid
, alu
)
121 self
.alu_name
= name
or "alu"
122 self
.opsubsetkls
= opsubsetkls
123 self
.cu
= cu
= CompUnitRecord(opsubsetkls
, rwid
, n_src
, n_dst
,
125 n_src
, n_dst
= self
.n_src
, self
.n_dst
= cu
._n
_src
, cu
._n
_dst
126 print("n_src %d n_dst %d" % (self
.n_src
, self
.n_dst
))
128 # convenience names for src operands
129 for i
in range(n_src
):
130 j
= i
+ 1 # name numbering to match src1/src2
132 setattr(self
, name
, getattr(cu
, name
))
134 # convenience names for dest operands
135 for i
in range(n_dst
):
136 j
= i
+ 1 # name numbering to match dest1/2...
137 name
= "dest%d_o" % j
138 setattr(self
, name
, getattr(cu
, name
))
140 # more convenience names
143 self
.rdmaskn
= cu
.rdmaskn
144 self
.wrmask
= cu
.wrmask
145 self
.go_rd_i
= self
.rd
.go_i
# temporary naming
146 self
.go_wr_i
= self
.wr
.go_i
# temporary naming
147 self
.rd_rel_o
= self
.rd
.rel_o
# temporary naming
148 self
.req_rel_o
= self
.wr
.rel_o
# temporary naming
149 self
.issue_i
= cu
.issue_i
150 self
.shadown_i
= cu
.shadown_i
151 self
.go_die_i
= cu
.go_die_i
153 # operation / data input
154 self
.oper_i
= cu
.oper_i
155 self
.src_i
= cu
._src
_i
157 self
.busy_o
= cu
.busy_o
159 self
.data_o
= self
.dest
[0] # Dest out
160 self
.done_o
= cu
.done_o
162 def _mux_op(self
, m
, sl
, op_is_imm
, imm
, i
):
163 # select imm if opcode says so. however also change the latch
164 # to trigger *from* the opcode latch instead.
165 src_or_imm
= Signal(self
.cu
._get
_srcwid
(i
), reset_less
=True)
166 src_sel
= Signal(reset_less
=True)
167 m
.d
.comb
+= src_sel
.eq(Mux(op_is_imm
, self
.opc_l
.q
, self
.src_l
.q
[i
]))
168 m
.d
.comb
+= src_or_imm
.eq(Mux(op_is_imm
, imm
, self
.src_i
[i
]))
169 # overwrite 1st src-latch with immediate-muxed stuff
170 sl
[i
][0] = src_or_imm
172 sl
[i
][3] = ~op_is_imm
# change rd.rel[i] gate condition
174 def elaborate(self
, platform
):
176 setattr(m
.submodules
, self
.alu_name
, self
.alu
)
177 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
178 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
179 m
.submodules
.req_l
= req_l
= SRLatch(False, self
.n_dst
, name
="req")
180 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
181 m
.submodules
.rok_l
= rok_l
= SRLatch(sync
=False, name
="rdok")
182 self
.opc_l
, self
.src_l
= opc_l
, src_l
184 # ALU only proceeds when all src are ready. rd_rel_o is delayed
185 # so combine it with go_rd_i. if all bits are set we're good
186 all_rd
= Signal(reset_less
=True)
187 m
.d
.comb
+= all_rd
.eq(self
.busy_o
& rok_l
.q
&
188 (((~self
.rd
.rel_o
) | self
.rd
.go_i
).all()))
190 # generate read-done pulse
191 all_rd_dly
= Signal(reset_less
=True)
192 all_rd_pulse
= Signal(reset_less
=True)
193 m
.d
.sync
+= all_rd_dly
.eq(all_rd
)
194 m
.d
.comb
+= all_rd_pulse
.eq(all_rd
& ~all_rd_dly
)
196 # create rising pulse from alu valid condition.
197 alu_done
= Signal(reset_less
=True)
198 alu_done_dly
= Signal(reset_less
=True)
199 alu_pulse
= Signal(reset_less
=True)
200 alu_pulsem
= Signal(self
.n_dst
, reset_less
=True)
201 m
.d
.comb
+= alu_done
.eq(self
.alu
.n
.valid_o
)
202 m
.d
.sync
+= alu_done_dly
.eq(alu_done
)
203 m
.d
.comb
+= alu_pulse
.eq(alu_done
& ~alu_done_dly
)
204 m
.d
.comb
+= alu_pulsem
.eq(Repl(alu_pulse
, self
.n_dst
))
206 # sigh bug where req_l gets both set and reset raised at same time
207 prev_wr_go
= Signal(self
.n_dst
)
208 brd
= Repl(self
.busy_o
, self
.n_dst
)
209 m
.d
.sync
+= prev_wr_go
.eq(self
.wr
.go_i
& brd
)
211 # write_requests all done
212 # req_done works because any one of the last of the writes
213 # is enough, when combined with when read-phase is done (rst_l.q)
214 wr_any
= Signal(reset_less
=True)
215 req_done
= Signal(reset_less
=True)
216 m
.d
.comb
+= self
.done_o
.eq(self
.busy_o
&
217 ~
((self
.wr
.rel_o
& ~self
.wrmask
).bool()))
218 m
.d
.comb
+= wr_any
.eq(self
.wr
.go_i
.bool() | prev_wr_go
.bool())
219 m
.d
.comb
+= req_done
.eq(wr_any
& ~self
.alu
.n
.ready_i
&
220 ((req_l
.q
& self
.wrmask
) == 0))
221 # argh, complicated hack: if there are no regs to write,
222 # instead of waiting for regs that are never going to happen,
223 # we indicate "done" when the ALU is "done"
224 with m
.If((self
.wrmask
== 0) &
225 self
.alu
.n
.ready_i
& self
.alu
.n
.valid_o
& self
.busy_o
):
226 m
.d
.comb
+= req_done
.eq(1)
229 reset
= Signal(reset_less
=True)
230 rst_r
= Signal(reset_less
=True) # reset latch off
231 reset_w
= Signal(self
.n_dst
, reset_less
=True)
232 reset_r
= Signal(self
.n_src
, reset_less
=True)
233 m
.d
.comb
+= reset
.eq(req_done | self
.go_die_i
)
234 m
.d
.comb
+= rst_r
.eq(self
.issue_i | self
.go_die_i
)
235 m
.d
.comb
+= reset_w
.eq(self
.wr
.go_i |
Repl(self
.go_die_i
, self
.n_dst
))
236 m
.d
.comb
+= reset_r
.eq(self
.rd
.go_i |
Repl(self
.go_die_i
, self
.n_src
))
238 # read-done,wr-proceed latch
239 m
.d
.comb
+= rok_l
.s
.eq(self
.issue_i
) # set up when issue starts
240 m
.d
.sync
+= rok_l
.r
.eq(self
.alu
.n
.valid_o
& self
.busy_o
) # ALU done
242 # wr-done, back-to-start latch
243 m
.d
.comb
+= rst_l
.s
.eq(all_rd
) # set when read-phase is fully done
244 m
.d
.comb
+= rst_l
.r
.eq(rst_r
) # *off* on issue
246 # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
247 m
.d
.sync
+= opc_l
.s
.eq(self
.issue_i
) # set on issue
248 m
.d
.sync
+= opc_l
.r
.eq(req_done
) # reset on ALU
250 # src operand latch (not using go_wr_i)
251 m
.d
.sync
+= src_l
.s
.eq(Repl(self
.issue_i
, self
.n_src
))
252 m
.d
.sync
+= src_l
.r
.eq(reset_r
)
254 # dest operand latch (not using issue_i)
255 m
.d
.comb
+= req_l
.s
.eq(alu_pulsem
& self
.wrmask
)
256 m
.d
.sync
+= req_l
.r
.eq(reset_w | prev_wr_go
)
258 # create a latch/register for the operand
259 oper_r
= self
.opsubsetkls(name
="oper_r")
260 latchregister(m
, self
.oper_i
, oper_r
, self
.issue_i
, "oper_l")
262 # and for each output from the ALU: capture when ALU output is valid
265 for i
in range(self
.n_dst
):
266 name
= "data_r%d" % i
267 lro
= self
.get_out(i
)
269 if isinstance(lro
, Record
):
270 data_r
= Record
.like(lro
, name
=name
)
271 print("wr fields", i
, lro
, data_r
.fields
)
272 # bye-bye abstract interface design..
273 fname
= find_ok(data_r
.fields
)
277 data_r
= Signal
.like(lro
, name
=name
, reset_less
=True)
278 wrok
.append(ok
& self
.busy_o
)
279 latchregister(m
, lro
, data_r
, alu_pulsem
, name
+ "_l")
282 # ok, above we collated anything with an "ok" on the output side
283 # now actually use those to create a write-mask. this basically
284 # is now the Function Unit API tells the Comp Unit "do not request
285 # a regfile port because this particular output is not valid"
286 m
.d
.comb
+= self
.wrmask
.eq(Cat(*wrok
))
288 # pass operation to the ALU (sync because time to wait for src reads)
289 m
.d
.sync
+= self
.get_op().eq(oper_r
)
291 # create list of src/alu-src/src-latch. override 1st and 2nd one below.
292 # in the case, for ALU and Logical pipelines, we assume RB is the
293 # 2nd operand in the input "regspec". see for example
294 # soc.fu.alu.pipe_data.ALUInputData
296 print("src_i", self
.src_i
)
297 for i
in range(self
.n_src
):
298 sl
.append([self
.src_i
[i
], self
.get_in(i
), src_l
.q
[i
], Const(1, 1)])
300 # if the operand subset has "zero_a" we implicitly assume that means
301 # src_i[0] is an INT reg type where zero can be multiplexed in, instead.
302 # see https://bugs.libre-soc.org/show_bug.cgi?id=336
303 if hasattr(oper_r
, "zero_a"):
304 # select zero imm if opcode says so. however also change the latch
305 # to trigger *from* the opcode latch instead.
306 self
._mux
_op
(m
, sl
, oper_r
.zero_a
, 0, 0)
308 # if the operand subset has "imm_data" we implicitly assume that means
309 # "this is an INT ALU/Logical FU jobbie, RB is muxed with the immediate"
310 if hasattr(oper_r
, "imm_data"):
311 # select immediate if opcode says so. however also change the latch
312 # to trigger *from* the opcode latch instead.
313 op_is_imm
= oper_r
.imm_data
.imm_ok
314 imm
= oper_r
.imm_data
.imm
315 self
._mux
_op
(m
, sl
, op_is_imm
, imm
, 1)
317 # create a latch/register for src1/src2 (even if it is a copy of imm)
318 for i
in range(self
.n_src
):
319 src
, alusrc
, latch
, _
= sl
[i
]
320 latchregister(m
, src
, alusrc
, latch
, name
="src_r%d" % i
)
323 # ALU connection / interaction
326 # on a go_read, tell the ALU we're accepting data.
327 m
.submodules
.alui_l
= alui_l
= SRLatch(False, name
="alui")
328 m
.d
.comb
+= self
.alu
.p
.valid_i
.eq(alui_l
.q
)
329 m
.d
.sync
+= alui_l
.r
.eq(self
.alu
.p
.ready_o
& alui_l
.q
)
330 m
.d
.comb
+= alui_l
.s
.eq(all_rd_pulse
)
332 # ALU output "ready" side. alu "ready" indication stays hi until
334 m
.submodules
.alu_l
= alu_l
= SRLatch(False, name
="alu")
335 m
.d
.comb
+= self
.alu
.n
.ready_i
.eq(alu_l
.q
)
336 m
.d
.sync
+= alu_l
.r
.eq(self
.alu
.n
.valid_o
& alu_l
.q
)
337 m
.d
.comb
+= alu_l
.s
.eq(all_rd_pulse
)
343 slg
= Cat(*map(lambda x
: x
[3], sl
)) # get req gate conditions
344 # all request signals gated by busy_o. prevents picker problems
345 m
.d
.comb
+= self
.busy_o
.eq(opc_l
.q
) # busy out
347 # read-release gated by busy (and read-mask)
348 bro
= Repl(self
.busy_o
, self
.n_src
)
349 m
.d
.comb
+= self
.rd
.rel_o
.eq(src_l
.q
& bro
& slg
& ~self
.rdmaskn
)
351 # write-release gated by busy and by shadow (and write-mask)
352 brd
= Repl(self
.busy_o
& self
.shadown_i
, self
.n_dst
)
353 m
.d
.comb
+= self
.wr
.rel_o
.eq(req_l
.q
& brd
& self
.wrmask
)
355 # output the data from the latch on go_write
356 for i
in range(self
.n_dst
):
357 with m
.If(self
.wr
.go_i
[i
] & self
.busy_o
):
358 m
.d
.comb
+= self
.dest
[i
].eq(drl
[i
])
362 def get_fu_out(self
, i
):
371 yield from self
.oper_i
.ports()