src/soc/experiment/compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 from nmigen.compat.sim import run_simulation
  14 from nmigen.cli import verilog, rtlil
  15 from nmigen import Module, Signal, Mux, Elaboratable, Repl, Array, Record, Const
  16 from nmigen.hdl.rec import (DIR_FANIN, DIR_FANOUT)
  17
  18 from nmutil.latch import SRLatch, latchregister
  19 from nmutil.iocontrol import RecordObject
  20
  21 from soc.decoder.power_decoder2 import Data
  22 from soc.decoder.power_enums import InternalOp
  23 from soc.fu.regspec import RegSpec, RegSpecALUAPI
  24
  25
  26 def go_record(n, name):
  27     r = Record([('go', n, DIR_FANIN),
  28                 ('rel', n, DIR_FANOUT)], name=name)
  29     r.go.reset_less = True
  30     r.rel.reset_less = True
  31     return r
  32
  33 # see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
  34
  35 class CompUnitRecord(RegSpec, RecordObject):
  36     """CompUnitRecord
  37
  38     base class for Computation Units, to provide a uniform API
  39     and allow "record.connect" etc. to be used, particularly when
  40     it comes to connecting multiple Computation Units up as a block
  41     (very laborious)
  42
  43     LDSTCompUnitRecord should derive from this class and add the
  44     additional signals it requires
  45
  46     :subkls:      the class (not an instance) needed to construct the opcode
  47     :rwid:        either an integer (specifies width of all regs) or a "regspec"
  48
  49     see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
  50     """
  51     def __init__(self, subkls, rwid, n_src=None, n_dst=None, name=None):
  52         RegSpec.__init__(self, rwid, n_src, n_dst)
  53         RecordObject.__init__(self, name)
  54         self._subkls = subkls
  55
  56         # create source operands
  57         src = []
  58         for i in range(n_src):
  59             j = i + 1 # name numbering to match src1/src2
  60             name = "src%d_i" % j
  61             rw = self._get_srcwid(i)
  62             sreg = Signal(rw, name=name, reset_less=True)
  63             setattr(self, name, sreg)
  64             src.append(sreg)
  65         self._src_i = src
  66
  67         # create dest operands
  68         dst = []
  69         for i in range(n_dst):
  70             j = i + 1 # name numbering to match dest1/2...
  71             name = "dest%d_i" % j
  72             rw = self._get_dstwid(i)
  73             dreg = Signal(rw, name=name, reset_less=True)
  74             setattr(self, name, dreg)
  75             dst.append(dreg)
  76         self._dest = dst
  77
  78         # operation / data input
  79         self.oper_i = subkls(name="oper_i") # operand
  80
  81         # create read/write and other scoreboard signalling
  82         self.rd = go_record(n_src, name="rd") # read in, req out
  83         self.wr = go_record(n_dst, name="wr") # write in, req out
  84         self.issue_i = Signal(reset_less=True) # fn issue in
  85         self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
  86         self.go_die_i = Signal() # go die (reset)
  87
  88         # output (busy/done)
  89         self.busy_o = Signal(reset_less=True) # fn busy out
  90         self.done_o = Signal(reset_less=True)
  91
  92
  93 class MultiCompUnit(RegSpecALUAPI, Elaboratable):
  94     def __init__(self, rwid, alu, opsubsetkls, n_src=2, n_dst=1):
  95         """MultiCompUnit
  96
  97         * :rwid:        width of register latches (TODO: allocate per regspec)
  98         * :alu:         the ALU (pipeline, FSM) - must conform to nmutil Pipe API
  99         * :opsubsetkls: the subset of Decode2ExecuteType
 100         * :n_src:       number of src operands
 101         * :n_dst:       number of destination operands
 102         """
 103         RegSpecALUAPI.__init__(self, rwid, alu)
 104         self.n_src, self.n_dst = n_src, n_dst
 105         self.opsubsetkls = opsubsetkls
 106         self.cu = cu = CompUnitRecord(opsubsetkls, rwid, n_src, n_dst)
 107
 108         # convenience names for src operands
 109         for i in range(n_src):
 110             j = i + 1 # name numbering to match src1/src2
 111             name = "src%d_i" % j
 112             setattr(self, name, getattr(cu, name))
 113
 114         # convenience names for dest operands
 115         for i in range(n_dst):
 116             j = i + 1 # name numbering to match dest1/2...
 117             name = "dest%d_i" % j
 118             setattr(self, name, getattr(cu, name))
 119
 120         # more convenience names
 121         self.rd = cu.rd
 122         self.wr = cu.wr
 123         self.go_rd_i = self.rd.go # temporary naming
 124         self.go_wr_i = self.wr.go # temporary naming
 125         self.rd_rel_o = self.rd.rel # temporary naming
 126         self.req_rel_o = self.wr.rel # temporary naming
 127         self.issue_i = cu.issue_i
 128         self.shadown_i = cu.shadown_i
 129         self.go_die_i = cu.go_die_i
 130
 131         # operation / data input
 132         self.oper_i = cu.oper_i
 133         self.src_i = cu._src_i
 134
 135         self.busy_o = cu.busy_o
 136         self.dest = cu._dest
 137         self.data_o = self.dest[0] # Dest out
 138         self.done_o = cu.done_o
 139
 140
 141     def _mux_op(self, m, sl, op_is_imm, imm, i):
 142         # select zero immediate if opcode says so.  however also change the latch
 143         # to trigger *from* the opcode latch instead.
 144         src_or_imm = Signal(self.cu._get_srcwid(i), reset_less=True)
 145         src_sel = Signal(reset_less=True)
 146         m.d.comb += src_sel.eq(Mux(op_is_imm, self.opc_l.q, self.src_l.q[i]))
 147         m.d.comb += src_or_imm.eq(Mux(op_is_imm, imm, self.src_i[i]))
 148         # overwrite 1st src-latch with immediate-muxed stuff
 149         sl[i][0] = src_or_imm
 150         sl[i][2] = src_sel
 151
 152     def elaborate(self, platform):
 153         m = Module()
 154         m.submodules.alu = self.alu
 155         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 156         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 157         m.submodules.req_l = req_l = SRLatch(False, self.n_dst, name="req")
 158         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 159         m.submodules.rok_l = rok_l = SRLatch(sync=False, name="rdok")
 160         self.opc_l, self.src_l = opc_l, src_l
 161
 162         # ALU only proceeds when all src are ready.  rd_rel_o is delayed
 163         # so combine it with go_rd_i.  if all bits are set we're good
 164         all_rd = Signal(reset_less=True)
 165         m.d.comb += all_rd.eq(self.busy_o & rok_l.q &
 166                     (((~self.rd.rel) | self.rd.go).all()))
 167
 168         # write_requests all done
 169         # req_done works because any one of the last of the writes
 170         # is enough, when combined with when read-phase is done (rst_l.q)
 171         wr_any = Signal(reset_less=True)
 172         req_done = Signal(reset_less=True)
 173         m.d.comb += self.done_o.eq(self.busy_o & ~(self.wr.rel.bool()))
 174         m.d.comb += wr_any.eq(self.wr.go.bool())
 175         m.d.comb += req_done.eq(rst_l.q & wr_any)
 176
 177         # shadow/go_die
 178         reset = Signal(reset_less=True)
 179         rst_r = Signal(reset_less=True) # reset latch off
 180         reset_w = Signal(self.n_dst, reset_less=True)
 181         reset_r = Signal(self.n_src, reset_less=True)
 182         m.d.comb += reset.eq(req_done | self.go_die_i)
 183         m.d.comb += rst_r.eq(self.issue_i | self.go_die_i)
 184         m.d.comb += reset_w.eq(self.wr.go | Repl(self.go_die_i, self.n_dst))
 185         m.d.comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
 186
 187         # read-done,wr-proceed latch
 188         m.d.comb += rok_l.s.eq(self.issue_i)  # set up when issue starts
 189         m.d.comb += rok_l.r.eq(self.alu.p.ready_o) # off when ALU acknowledges
 190
 191         # wr-done, back-to-start latch
 192         m.d.comb += rst_l.s.eq(all_rd)     # set when read-phase is fully done
 193         m.d.comb += rst_l.r.eq(rst_r)        # *off* on issue
 194
 195         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
 196         m.d.sync += opc_l.s.eq(self.issue_i)       # set on issue
 197         m.d.sync += opc_l.r.eq(self.alu.n.valid_o & req_done) # reset on ALU
 198
 199         # src operand latch (not using go_wr_i)
 200         m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src))
 201         m.d.sync += src_l.r.eq(reset_r)
 202
 203         # dest operand latch (not using issue_i)
 204         m.d.sync += req_l.s.eq(Repl(all_rd, self.n_dst))
 205         m.d.sync += req_l.r.eq(reset_w)
 206
 207         # create a latch/register for the operand
 208         oper_r = self.opsubsetkls(name="oper_r")
 209         latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_l")
 210
 211         # and for each output from the ALU
 212         drl = []
 213         for i in range(self.n_dst):
 214             name = "data_r%d" % i
 215             data_r = Signal(self.cu._get_srcwid(i), name=name, reset_less=True)
 216             latchregister(m, self.get_out(i), data_r, req_l.q[i], name + "_l")
 217             drl.append(data_r)
 218
 219         # pass the operation to the ALU
 220         m.d.comb += self.get_op().eq(oper_r)
 221
 222         # create list of src/alu-src/src-latch.  override 1st and 2nd one below.
 223         # in the case, for ALU and Logical pipelines, we assume RB is the 2nd operand
 224         # in the input "regspec".  see for example soc.fu.alu.pipe_data.ALUInputData
 225         sl = []
 226         for i in range(self.n_src):
 227             sl.append([self.src_i[i], self.get_in(i), src_l.q[i]])
 228
 229         # if the operand subset has "zero_a" we implicitly assume that means
 230         # src_i[0] is an INT register type where zero can be multiplexed in, instead.
 231         # see https://bugs.libre-soc.org/show_bug.cgi?id=336
 232         if hasattr(oper_r, "zero_a"):
 233             # select zero immediate if opcode says so.  however also change the latch
 234             # to trigger *from* the opcode latch instead.
 235             self._mux_op(m, sl, oper_r.zero_a, 0, 0)
 236
 237         # if the operand subset has "imm_data" we implicitly assume that means
 238         # "this is an INT ALU/Logical FU jobbie, RB is multiplexed with the immediate"
 239         if hasattr(oper_r, "imm_data"):
 240             # select immediate if opcode says so.  however also change the latch
 241             # to trigger *from* the opcode latch instead.
 242             op_is_imm = oper_r.imm_data.imm_ok
 243             imm = oper_r.imm_data.imm
 244             self._mux_op(m, sl, op_is_imm, imm, 1)
 245
 246         # create a latch/register for src1/src2 (even if it is a copy of an immediate)
 247         for i in range(self.n_src):
 248             src, alusrc, latch = sl[i]
 249             latchregister(m, src, alusrc, latch, name="src_r%d" % i)
 250
 251         # -----
 252         # outputs
 253         # -----
 254
 255         # all request signals gated by busy_o.  prevents picker problems
 256         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 257         bro = Repl(self.busy_o, self.n_src)
 258         m.d.comb += self.rd.rel.eq(src_l.q & bro) # src1/src2 req rel
 259
 260         # on a go_read, tell the ALU we're accepting data.
 261         # NOTE: this spells TROUBLE if the ALU isn't ready!
 262         # go_read is only valid for one clock!
 263         with m.If(all_rd):                           # src operands ready, GO!
 264             with m.If(~self.alu.p.ready_o):          # no ACK yet
 265                 m.d.comb += self.alu.p.valid_i.eq(1) # so indicate valid
 266
 267         brd = Repl(self.busy_o & self.shadown_i, self.n_dst)
 268         # only proceed if ALU says its output is valid
 269         with m.If(self.alu.n.valid_o):
 270             # when ALU ready, write req release out. waits for shadow
 271             m.d.comb += self.wr.rel.eq(req_l.q & brd)
 272             # when output latch is ready, and ALU says ready, accept ALU output
 273             with m.If(reset):
 274                 m.d.comb += self.alu.n.ready_i.eq(1) # tells ALU "thanks got it"
 275
 276         # output the data from the latch on go_write
 277         for i in range(self.n_dst):
 278             with m.If(self.wr.go[i]):
 279                 m.d.comb += self.dest[i].eq(drl[i])
 280
 281         return m
 282
 283     def __iter__(self):
 284         yield self.rd.go
 285         yield self.wr.go
 286         yield self.issue_i
 287         yield self.shadown_i
 288         yield self.go_die_i
 289         yield from self.oper_i.ports()
 290         yield self.src1_i
 291         yield self.src2_i
 292         yield self.busy_o
 293         yield self.rd.rel
 294         yield self.wr.rel
 295         yield self.data_o
 296
 297     def ports(self):
 298         return list(self)
 299
 300
 301 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
 302     yield dut.issue_i.eq(0)
 303     yield
 304     yield dut.src_i[0].eq(a)
 305     yield dut.src_i[1].eq(b)
 306     yield dut.oper_i.insn_type.eq(op)
 307     yield dut.oper_i.invert_a.eq(inv_a)
 308     yield dut.oper_i.imm_data.imm.eq(imm)
 309     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 310     yield dut.oper_i.zero_a.eq(zero_a)
 311     yield dut.issue_i.eq(1)
 312     yield
 313     yield dut.issue_i.eq(0)
 314     yield
 315     yield dut.rd.go.eq(0b11)
 316     while True:
 317         yield
 318         rd_rel_o = yield dut.rd.rel
 319         print ("rd_rel", rd_rel_o)
 320         if rd_rel_o:
 321             break
 322     yield
 323     yield dut.rd.go.eq(0)
 324     req_rel_o = yield dut.wr.rel
 325     result = yield dut.data_o
 326     print ("req_rel", req_rel_o, result)
 327     while True:
 328         req_rel_o = yield dut.wr.rel
 329         result = yield dut.data_o
 330         print ("req_rel", req_rel_o, result)
 331         if req_rel_o:
 332             break
 333         yield
 334     yield dut.wr.go[0].eq(1)
 335     yield
 336     result = yield dut.data_o
 337     print ("result", result)
 338     yield dut.wr.go[0].eq(0)
 339     yield
 340     return result
 341
 342
 343 def scoreboard_sim(dut):
 344     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
 345                                     imm=8, imm_ok=1)
 346     assert result == 13
 347
 348     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
 349     assert result == 7
 350
 351     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
 352     assert result == 65532
 353
 354     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1,
 355                                     imm=8, imm_ok=1)
 356     assert result == 8
 357
 358     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1)
 359     assert result == 2
 360
 361
 362 def test_compunit():
 363     from alu_hier import ALU
 364     from soc.fu.alu.alu_input_record import CompALUOpSubset
 365
 366     m = Module()
 367     alu = ALU(16)
 368     dut = MultiCompUnit(16, alu, CompALUOpSubset)
 369     m.submodules.cu = dut
 370
 371     vl = rtlil.convert(dut, ports=dut.ports())
 372     with open("test_compunit1.il", "w") as f:
 373         f.write(vl)
 374
 375     run_simulation(m, scoreboard_sim(dut), vcd_name='test_compunit1.vcd')
 376
 377
 378 def test_compunit_regspec1():
 379     from alu_hier import ALU
 380     from soc.fu.alu.alu_input_record import CompALUOpSubset
 381
 382     inspec = [('INT', 'a', '0:15'),
 383               ('INT', 'b', '0:15')]
 384     outspec = [('INT', 'o', '0:15'),
 385               ]
 386
 387     regspec = (inspec, outspec)
 388
 389     m = Module()
 390     alu = ALU(16)
 391     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 392     m.submodules.cu = dut
 393
 394     vl = rtlil.convert(dut, ports=dut.ports())
 395     with open("test_compunit_regspec1.il", "w") as f:
 396         f.write(vl)
 397
 398     run_simulation(m, scoreboard_sim(dut), vcd_name='test_compunit_regspec1.vcd')
 399
 400
 401 if __name__ == '__main__':
 402     test_compunit()
 403     test_compunit_regspec1()