src/soc/experiment/compldst_multi.py

   1 """ LOAD / STORE Computation Unit.
   2
   3     This module covers POWER9-compliant Load and Store operations,
   4     with selection on each between immediate and indexed mode as
   5     options for the calculation of the Effective Address (EA),
   6     and also "update" mode which optionally stores that EA into
   7     an additional register.
   8
   9     ----
  10     Note: it took 15 attempts over several weeks to redraw the diagram
  11     needed to capture this FSM properly.  To understand it fully, please
  12     take the time to review the links, video, and diagram.
  13     ----
  14
  15     Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
  16     compute the "Effective Address", and, when ready the operand (src3_i)
  17     is stored in the computed address (passed through to the PortInterface)
  18
  19     Loads are activated when Go_Write[0] is enabled.  The EA is computed,
  20     and (as long as there was no exception) the data comes out (at any
  21     time from the PortInterface), and is captured by the LDCompSTUnit.
  22
  23     Both LD and ST may request that the address be computed from summing
  24     operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
  25     the immediate (from the opcode).
  26
  27     Both LD and ST may also request "update" mode (op_is_update) which
  28     activates the use of Go_Write[1] to control storage of the EA into
  29     a *second* operand in the register file.
  30
  31     Thus this module has *TWO* write-requests to the register file and
  32     *THREE* read-requests to the register file (not all at the same time!)
  33     The regfile port usage is:
  34
  35     * LD-imm         1R1W
  36     * LD-imm-update  1R2W
  37     * LD-idx         2R1W
  38     * LD-idx-update  2R2W
  39
  40     * ST-imm         2R
  41     * ST-imm-update  2R1W
  42     * ST-idx         3R
  43     * ST-idx-update  3R1W
  44
  45     It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
  46     is not suited to (nmigen.FSM is clock-driven, and some aspects of
  47     the nested FSMs below are *combinatorial*).
  48
  49     * One FSM covers Operand collection and communication address-side
  50       with the LD/ST PortInterface.  its role ends when "RD_DONE" is asserted
  51
  52     * A second FSM activates to cover LD.  it activates if op_is_ld is true
  53
  54     * A third FSM activates to cover ST.  it activates if op_is_st is true
  55
  56     * The "overall" (fourth) FSM coordinates the progression and completion
  57       of the three other FSMs, firing "WR_RESET" which switches off "busy"
  58
  59     Full diagram:
  60     https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
  61
  62     Links including to walk-through videos:
  63     * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
  64
  65     Related Bugreports:
  66     * https://bugs.libre-soc.org/show_bug.cgi?id=302
  67
  68     Terminology:
  69
  70     * EA - Effective Address
  71     * LD - Load
  72     * ST - Store
  73 """
  74
  75 from nmigen.compat.sim import run_simulation
  76 from nmigen.cli import verilog, rtlil
  77 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
  78 from nmigen.hdl.rec import Record, Layout
  79
  80 from nmutil.latch import SRLatch, latchregister
  81
  82 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  83 from soc.experiment.l0_cache import PortInterface
  84 from soc.experiment.testmem import TestMemory
  85
  86 from soc.decoder.power_enums import InternalOp, Function
  87 from fu.ldst.ldst_input_record import CompLDSTOpSubset
  88
  89
  90 class LDSTCompUnitRecord(CompUnitRecord):
  91     def __init__(self, rwid, name=None):
  92         CompUnitRecord.__init__(self, CompLDSTOpSubset, rwid,
  93                                 n_src=3, n_dst=2, name=name)
  94
  95         self.ad = go_record(1, name="ad") # address go in, req out
  96         self.st = go_record(1, name="st") # store go in, req out
  97
  98         self.addr_exc_o = Signal(reset_less=True)   # address exception
  99
 100         self.ld_o = Signal(reset_less=True)  # operation is a LD
 101         self.st_o = Signal(reset_less=True)  # operation is a ST
 102
 103         # hmm... are these necessary?
 104         self.load_mem_o = Signal(reset_less=True)  # activate memory LOAD
 105         self.stwd_mem_o = Signal(reset_less=True)  # activate memory STORE
 106
 107
 108 class LDSTCompUnit(Elaboratable):
 109     """LOAD / STORE Computation Unit
 110
 111     Inputs
 112     ------
 113
 114     * :pi:     a PortInterface to the memory subsystem (read-write capable)
 115     * :rwid:   register width
 116     * :awid:   address width
 117
 118     Data inputs
 119     -----------
 120     * :src_i:  Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
 121
 122     Data (outputs)
 123     --------------
 124     * :data_o:     Dest out (LD)          - managed by wr[0] go/req
 125     * :addr_o:     Address out (LD or ST) - managed by wr[1] go/req
 126     * :addr_exc_o: Address/Data Exception occurred.  LD/ST must terminate
 127
 128     TODO: make addr_exc_o a data-type rather than a single-bit signal
 129           (see bug #302)
 130
 131     Control Signals (In)
 132     --------------------
 133
 134     * :oper_i:     operation being carried out (POWER9 decode LD/ST subset)
 135     * :issue_i:    LD/ST is being "issued".
 136     * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
 137     * :go_rd_i:    read is being actioned (latches in src regs)
 138     * :go_wr_i:    write mode (exactly like ALU CompUnit)
 139     * :go_ad_i:    address is being actioned (triggers actual mem LD)
 140     * :go_st_i:    store is being actioned (triggers actual mem STORE)
 141     * :go_die_i:   resets the unit back to "wait for issue"
 142
 143     Control Signals (Out)
 144     ---------------------
 145
 146     * :busy_o:      function unit is busy
 147     * :rd_rel_o:    request src1/src2
 148     * :adr_rel_o:   request address (from mem)
 149     * :sto_rel_o:   request store (to mem)
 150     * :req_rel_o:   request write (result)
 151     * :load_mem_o:  activate memory LOAD
 152     * :stwd_mem_o:  activate memory STORE
 153
 154     Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
 155     in a single cycle and the CompUnit set back to doing another op.
 156     This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
 157     depending on whether the operation is a ST or LD.
 158     """
 159
 160     def __init__(self, pi, rwid=64, awid=48, debugtest=False):
 161         self.rwid = rwid
 162         self.awid = awid
 163         self.pi = pi
 164         self.cu = cu = LDSTCompUnitRecord(rwid)
 165         self.debugtest = debugtest
 166
 167         # POWER-compliant LD/ST has index and update: *fixed* number of ports
 168         self.n_src = n_src = 3   # RA, RB, RT/RS
 169         self.n_dst = n_dst = 2 # RA, RT/RS
 170
 171         # set up array of src and dest signals
 172         for i in range(n_src):
 173             j = i + 1 # name numbering to match src1/src2
 174             name = "src%d_i" % j
 175             setattr(self, name, getattr(cu, name))
 176
 177         dst = []
 178         for i in range(n_dst):
 179             j = i + 1 # name numbering to match dest1/2...
 180             name = "dest%d_i" % j
 181             setattr(self, name, getattr(cu, name))
 182
 183         # convenience names
 184         self.rd = cu.rd
 185         self.wr = cu.wr
 186         self.ad = cu.ad
 187         self.st = cu.st
 188
 189         self.go_rd_i = self.rd.go # temporary naming
 190         self.go_wr_i = self.wr.go # temporary naming
 191         self.go_ad_i = self.ad.go # temp naming: go address in
 192         self.go_st_i = self.st.go  # temp naming: go store in
 193
 194         self.rd_rel_o = self.rd.rel # temporary naming
 195         self.req_rel_o = self.wr.rel # temporary naming
 196         self.adr_rel_o = self.ad.rel  # request address (from mem)
 197         self.sto_rel_o = self.st.rel  # request store (to mem)
 198
 199         self.issue_i = cu.issue_i
 200         self.shadown_i = cu.shadown_i
 201         self.go_die_i = cu.go_die_i
 202
 203         self.oper_i = cu.oper_i
 204         self.src_i = cu._src_i
 205         self.dest = cu._dest
 206
 207         self.data_o = self.dest[0]  # Dest1 out: RT
 208         self.addr_o = self.dest[1]  # Address out (LD or ST) - Update => RA
 209         self.addr_exc_o = cu.addr_exc_o
 210         self.done_o = cu.done_o
 211         self.busy_o = cu.busy_o
 212
 213         self.ld_o = cu.ld_o
 214         self.st_o = cu.st_o
 215
 216         self.load_mem_o = cu.load_mem_o
 217         self.stwd_mem_o = cu.stwd_mem_o
 218
 219     def elaborate(self, platform):
 220         m = Module()
 221
 222         # temp/convenience
 223         comb = m.d.comb
 224         sync = m.d.sync
 225         issue_i = self.issue_i
 226
 227         #####################
 228         # latches for the FSM.
 229         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 230         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 231         m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
 232         m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
 233         m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
 234         m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
 235         m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
 236         m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
 237         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 238
 239         ####################
 240         # signals
 241
 242         # opcode decode
 243         op_is_ld = Signal(reset_less=True)
 244         op_is_st = Signal(reset_less=True)
 245
 246         # ALU/LD data output control
 247         alu_valid = Signal(reset_less=True) # ALU operands are valid
 248         alu_ok = Signal(reset_less=True)    # ALU out ok (1 clock delay valid)
 249         addr_ok = Signal(reset_less=True)   # addr ok (from PortInterface)
 250         ld_ok = Signal(reset_less=True)     # LD out ok from PortInterface
 251         wr_any = Signal(reset_less=True)    # any write (incl. store)
 252         rda_any = Signal(reset_less=True)   # any read for address ops
 253         rd_done = Signal(reset_less=True)   # all *necessary* operands read
 254         wr_reset = Signal(reset_less=True)  # final reset condition
 255
 256         # LD and ALU out
 257         alu_o = Signal(self.rwid, reset_less=True)
 258         ldd_o = Signal(self.rwid, reset_less=True)
 259
 260         # select immediate or src2 reg to add
 261         src2_or_imm = Signal(self.rwid, reset_less=True)
 262         src_sel = Signal(reset_less=True)
 263
 264         ##############################
 265         # reset conditions for latches
 266
 267         # temporaries (also convenient when debugging)
 268         reset_o = Signal(reset_less=True)             # reset opcode
 269         reset_w = Signal(reset_less=True)             # reset write
 270         reset_u = Signal(reset_less=True)             # reset update
 271         reset_a = Signal(reset_less=True)             # reset adr latch
 272         reset_i = Signal(reset_less=True)             # issue|die (use a lot)
 273         reset_r = Signal(self.n_src, reset_less=True) # reset src
 274         reset_s = Signal(reset_less=True)             # reset store
 275
 276         comb += reset_i.eq(issue_i | self.go_die_i)       # various
 277         comb += reset_o.eq(wr_reset | self.go_die_i)      # opcode reset
 278         comb += reset_w.eq(self.wr.go[0] | self.go_die_i) # write reg 1
 279         comb += reset_u.eq(self.wr.go[1] | self.go_die_i) # update (reg 2)
 280         comb += reset_s.eq(self.go_st_i | self.go_die_i)  # store reset
 281         comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
 282         comb += reset_a.eq(self.go_ad_i | self.go_die_i)
 283
 284         ##########################
 285         # FSM implemented through sequence of latches.  approximately this:
 286         # - opc_l       : opcode
 287         #    - src_l[0] : operands
 288         #    - src_l[1]
 289         #       - alu_l : looks after add of src1/2/imm (EA)
 290         #       - adr_l : waits for add (EA)
 291         #       - upd_l : waits for adr and Regfile (port 2)
 292         #    - src_l[2] : ST
 293         # - lod_l       : waits for adr (EA) and for LD Data
 294         # - wri_l       : waits for LD Data and Regfile (port 1)
 295         # - st_l        : waits for alu and operand2
 296         # - rst_l       : waits for all FSM paths to converge.
 297         # NOTE: use sync to stop combinatorial loops.
 298
 299         # opcode latch - inverted so that busy resets to 0
 300         # note this MUST be sync so as to avoid a combinatorial loop
 301         # between busy_o and issue_i on the reset latch (rst_l)
 302         sync += opc_l.s.eq(issue_i)  # XXX NOTE: INVERTED FROM book!
 303         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 304
 305         # src operand latch
 306         sync += src_l.s.eq(Repl(issue_i, self.n_src))
 307         sync += src_l.r.eq(reset_r)
 308
 309         # alu latch.  use sync-delay between alu_ok and valid to generate pulse
 310         comb += alu_l.s.eq(reset_i)
 311         comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
 312
 313         # addr latch
 314         comb += adr_l.s.eq(reset_i)
 315         sync += adr_l.r.eq(reset_a)
 316
 317         # ld latch
 318         comb += lod_l.s.eq(reset_i)
 319         comb += lod_l.r.eq(ld_ok)
 320
 321         # dest operand latch
 322         comb += wri_l.s.eq(issue_i)
 323         sync += wri_l.r.eq(reset_w)
 324
 325         # update-mode operand latch (EA written to reg 2)
 326         sync += upd_l.s.eq(reset_i)
 327         sync += upd_l.r.eq(reset_u)
 328
 329         # store latch
 330         comb += sto_l.s.eq(addr_ok & op_is_st)
 331         comb += sto_l.r.eq(reset_s)
 332
 333         # reset latch
 334         comb += rst_l.s.eq(addr_ok) # start when address is ready
 335         comb += rst_l.r.eq(issue_i)
 336
 337         # create a latch/register for the operand
 338         oper_r = CompLDSTOpSubset()  # Dest register
 339         latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_r")
 340
 341         # and for LD
 342         ldd_r = Signal(self.rwid, reset_less=True)  # Dest register
 343         latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
 344
 345         # and for each input from the incoming src operands
 346         srl = []
 347         for i in range(self.n_src):
 348             name = "src_r%d" % i
 349             src_r = Signal(self.rwid, name=name, reset_less=True)
 350             latchregister(m, self.src_i[i], src_r, src_l.q[i], name)
 351             srl.append(src_r)
 352
 353         # and one for the output from the ADD (for the EA)
 354         addr_r = Signal(self.rwid, reset_less=True)  # Effective Address Latch
 355         latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
 356
 357         # select either immediate or src2 if opcode says so
 358         op_is_imm = oper_r.imm_data.imm_ok
 359         src2_or_imm = Signal(self.rwid, reset_less=True)
 360         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1]))
 361
 362         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
 363         sync += alu_o.eq(srl[0] + src2_or_imm) # actual EA
 364         sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
 365
 366         # decode bits of operand (latched)
 367         comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST
 368         comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD)  # LD
 369         op_is_update = oper_r.update                                 # UPDATE
 370         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 371         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 372         comb += self.ld_o.eq(op_is_ld)
 373         comb += self.st_o.eq(op_is_st)
 374
 375         ############################
 376         # Control Signal calculation
 377
 378         # busy signal
 379         busy_o = self.busy_o
 380         comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o)  # busy out
 381
 382         # 1st operand read-request is simple: always need it
 383         comb += self.rd.rel[0].eq(src_l.q[0] & busy_o)
 384
 385         # 2nd operand only needed when immediate is not active
 386         comb += self.rd.rel[1].eq(src_l.q[1] & busy_o & ~op_is_imm)
 387
 388         # note when the address-related read "go" signals are active
 389         comb += rda_any.eq(self.rd.go[0] | self.rd.go[1])
 390
 391         # alu input valid when 1st and 2nd ops done (or imm not active)
 392         comb += alu_valid.eq(busy_o & ~(self.rd.rel[0] | self.rd.rel[1]))
 393
 394         # 3rd operand only needed when operation is a store
 395         comb += self.rd.rel[2].eq(src_l.q[2] & busy_o & op_is_st)
 396
 397         # all reads done when alu is valid and 3rd operand needed
 398         comb += rd_done.eq(alu_valid & ~self.rd.rel[2])
 399
 400         # address release only if addr ready, but Port must be idle
 401         comb += self.adr_rel_o.eq(adr_l.q & busy_o)
 402
 403         # store release when st ready *and* all operands read (and no shadow)
 404         comb += self.st.rel.eq(sto_l.q & busy_o & rd_done & op_is_st &
 405                                self.shadown_i)
 406
 407         # request write of LD result.  waits until shadow is dropped.
 408         comb += self.wr.rel[0].eq(wri_l.q & busy_o & lod_l.qn & op_is_ld &
 409                                   self.shadown_i)
 410
 411         # request write of EA result only in update mode
 412         comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update &
 413                                   self.shadown_i)
 414
 415         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
 416         comb += wr_any.eq(self.st.go | self.wr.go[0] | self.wr.go[1])
 417         comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
 418                     ~(self.st.rel | self.wr.rel[0] | self.wr.rel[1]) &
 419                      (lod_l.qn | op_is_st))
 420         comb += self.done_o.eq(wr_reset)
 421
 422         ######################
 423         # Data/Address outputs
 424
 425         # put the LD-output register directly onto the output bus on a go_write
 426         with m.If(self.wr.go[0]):
 427             comb += self.data_o.eq(ldd_r)
 428
 429         # "update" mode, put address out on 2nd go-write
 430         with m.If(op_is_update & self.wr.go[1]):
 431             comb += self.addr_o.eq(addr_r)
 432
 433         ###########################
 434         # PortInterface connections
 435         pi = self.pi
 436
 437         # connect to LD/ST PortInterface.
 438         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD
 439         comb += pi.is_st_i.eq(op_is_st & busy_o)  # decoded-ST
 440         comb += pi.op.eq(self.oper_i)    # op details (not all needed)
 441         # address
 442         comb += pi.addr.data.eq(addr_r)           # EA from adder
 443         comb += pi.addr.ok.eq(alu_ok & lod_l.q) # "go do address stuff"
 444         comb += self.addr_exc_o.eq(pi.addr_exc_o) # exception occurred
 445         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 446         # ld - ld gets latched in via lod_l
 447         comb += ldd_o.eq(pi.ld.data)  # ld data goes into ld reg (above)
 448         comb += ld_ok.eq(pi.ld.ok) # ld.ok *closes* (freezes) ld data
 449         # store - data goes in based on go_st
 450         comb += pi.st.data.eq(srl[2]) # 3rd operand latch
 451         comb += pi.st.ok.eq(self.st.go)  # go store signals st data valid
 452
 453         return m
 454
 455     def __iter__(self):
 456         yield self.rd.go
 457         yield self.go_ad_i
 458         yield self.wr.go
 459         yield self.go_st_i
 460         yield self.issue_i
 461         yield self.shadown_i
 462         yield self.go_die_i
 463         yield from self.oper_i.ports()
 464         yield from self.src_i
 465         yield self.busy_o
 466         yield self.rd.rel
 467         yield self.adr_rel_o
 468         yield self.sto_rel_o
 469         yield self.wr.rel
 470         yield self.data_o
 471         yield self.addr_o
 472         yield self.load_mem_o
 473         yield self.stwd_mem_o
 474
 475     def ports(self):
 476         return list(self)
 477
 478
 479 def wait_for(sig, wait=True, test1st=False):
 480     v = (yield sig)
 481     print("wait for", sig, v, wait, test1st)
 482     if test1st and bool(v) == wait:
 483         return
 484     while True:
 485         yield
 486         v = (yield sig)
 487         #print("...wait for", sig, v)
 488         if bool(v) == wait:
 489             break
 490
 491
 492 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False):
 493     print ("ST", src1, src2, src3, imm, imm_ok, update)
 494     yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
 495     yield dut.src1_i.eq(src1)
 496     yield dut.src2_i.eq(src2)
 497     yield dut.src3_i.eq(src3)
 498     yield dut.oper_i.imm_data.imm.eq(imm)
 499     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 500     yield dut.oper_i.update.eq(update)
 501     yield dut.issue_i.eq(1)
 502     yield
 503     yield dut.issue_i.eq(0)
 504     yield
 505     if imm_ok:
 506         yield dut.rd.go.eq(0b101)
 507     else:
 508         yield dut.rd.go.eq(0b111)
 509     yield from wait_for(dut.rd.rel)
 510     yield dut.rd.go.eq(0)
 511
 512     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 513     #yield from wait_for(dut.adr_rel_o)
 514     #yield dut.ad.go.eq(1)
 515     #yield
 516     #yield dut.ad.go.eq(0)
 517
 518     if update:
 519         yield from wait_for(dut.wr.rel[1])
 520         yield dut.wr.go.eq(0b10)
 521         yield
 522         addr = yield dut.addr_o
 523         print ("addr", addr)
 524         yield dut.wr.go.eq(0)
 525     else:
 526         addr = None
 527
 528     yield from wait_for(dut.sto_rel_o)
 529     yield dut.go_st_i.eq(1)
 530     yield
 531     yield dut.go_st_i.eq(0)
 532     yield from wait_for(dut.busy_o, False)
 533     #wait_for(dut.stwd_mem_o)
 534     yield
 535     return addr
 536
 537
 538 def load(dut, src1, src2, imm, imm_ok=True, update=False):
 539     print ("LD", src1, src2, imm, imm_ok, update)
 540     yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
 541     yield dut.src1_i.eq(src1)
 542     yield dut.src2_i.eq(src2)
 543     yield dut.oper_i.imm_data.imm.eq(imm)
 544     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 545     yield dut.issue_i.eq(1)
 546     yield
 547     yield dut.issue_i.eq(0)
 548     yield
 549     if imm_ok:
 550         yield dut.rd.go.eq(0b01)
 551     else:
 552         yield dut.rd.go.eq(0b11)
 553     yield from wait_for(dut.rd.rel)
 554     yield dut.rd.go.eq(0)
 555
 556     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 557     #yield dut.ad.go.eq(1)
 558     #yield
 559     #yield dut.ad.go.eq(0)
 560
 561     if update:
 562         yield from wait_for(dut.wr.rel[1])
 563         yield dut.wr.go.eq(0b10)
 564         yield
 565         addr = yield dut.addr_o
 566         print ("addr", addr)
 567         yield dut.wr.go.eq(0)
 568     else:
 569         addr = None
 570
 571     yield from wait_for(dut.wr.rel[0], test1st=True)
 572     yield dut.wr.go.eq(1)
 573     yield
 574     data = yield dut.data_o
 575     print (data)
 576     yield dut.wr.go.eq(0)
 577     yield from wait_for(dut.busy_o)
 578     yield
 579     # wait_for(dut.stwd_mem_o)
 580     return data, addr
 581
 582
 583 def scoreboard_sim(dut):
 584
 585     ###################
 586     # immediate version
 587
 588     # two STs (different addresses)
 589     yield from store(dut, 4, 0, 3, 2)  # ST reg4 into addr rfile[reg3]+2
 590     yield from store(dut, 2, 0, 9, 2)  # ST reg4 into addr rfile[reg9]+2
 591     yield
 592     # two LDs (deliberately LD from the 1st address then 2nd)
 593     data, addr = yield from load(dut, 4, 0, 2)
 594     assert data == 0x0003, "returned %x" % data
 595     data, addr  = yield from load(dut, 2, 0, 2)
 596     assert data == 0x0009, "returned %x" % data
 597     yield
 598
 599     # indexed version
 600     yield from store(dut, 4, 5, 3, 0, imm_ok=False)
 601     data, addr = yield from load(dut, 4, 5, 0, imm_ok=False)
 602     assert data == 0x0003, "returned %x" % data
 603
 604     # update-immediate version
 605     addr = yield from store(dut, 4, 6, 3, 2, update=True)
 606     assert addr == 0x0006, "returned %x" % addr
 607
 608     # update-indexed version
 609     data, addr  = yield from load(dut, 4, 5, 0, imm_ok=False, update=True)
 610     assert addr == 0x0009, "returned %x" % addr
 611
 612 class TestLDSTCompUnit(LDSTCompUnit):
 613
 614     def __init__(self, rwid):
 615         from soc.experiment.l0_cache import TstL0CacheBuffer
 616         self.l0 = l0 = TstL0CacheBuffer()
 617         pi = l0.l0.dports[0].pi
 618         LDSTCompUnit.__init__(self, pi, rwid, 4)
 619
 620     def elaborate(self, platform):
 621         m = LDSTCompUnit.elaborate(self, platform)
 622         m.submodules.l0 = self.l0
 623         m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
 624         return m
 625
 626
 627 def test_scoreboard():
 628
 629     dut = TestLDSTCompUnit(16)
 630     vl = rtlil.convert(dut, ports=dut.ports())
 631     with open("test_ldst_comp.il", "w") as f:
 632         f.write(vl)
 633
 634     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_comp.vcd')
 635
 636
 637 if __name__ == '__main__':
 638     test_scoreboard()