1 """LOAD / STORE Computation Unit.
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
23 Both LD and ST may request that the address be computed from summing
24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
25 the immediate (from the opcode).
27 Both LD and ST may also request "update" mode (op_is_update) which
28 activates the use of Go_Write[1] to control storage of the EA into
29 a *second* operand in the register file.
31 Thus this module has *TWO* write-requests to the register file and
32 *THREE* read-requests to the register file (not all at the same time!)
33 The regfile port usage is:
45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
47 the nested FSMs below are *combinatorial*).
49 * One FSM covers Operand collection and communication address-side
50 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
52 * A second FSM activates to cover LD. it activates if op_is_ld is true
54 * A third FSM activates to cover ST. it activates if op_is_st is true
56 * The "overall" (fourth) FSM coordinates the progression and completion
57 of the three other FSMs, firing "WR_RESET" which switches off "busy"
61 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
63 Links including to walk-through videos:
65 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
66 * http://libre-soc.org/openpower/isa/fixedload
67 * http://libre-soc.org/openpower/isa/fixedstore
71 * https://bugs.libre-soc.org/show_bug.cgi?id=302
72 * https://bugs.libre-soc.org/show_bug.cgi?id=216
76 * EA - Effective Address
81 from nmigen
.compat
.sim
import run_simulation
82 from nmigen
.cli
import verilog
, rtlil
83 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
84 from nmigen
.hdl
.rec
import Record
, Layout
86 from nmutil
.latch
import SRLatch
, latchregister
87 from nmutil
.byterev
import byte_reverse
88 from nmutil
.extend
import exts
90 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
91 from soc
.experiment
.l0_cache
import PortInterface
92 from soc
.experiment
.pimem
import LDSTException
93 from soc
.fu
.regspec
import RegSpecAPI
95 from openpower
.decoder
.power_enums
import MicrOp
, Function
, LDSTMode
96 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
97 from openpower
.decoder
.power_decoder2
import Data
98 from openpower
.consts
import MSR
101 # TODO: LDSTInputData and LDSTOutputData really should be used
102 # here, to make things more like the other CompUnits. currently,
103 # also, RegSpecAPI is used explicitly here
106 class LDSTCompUnitRecord(CompUnitRecord
):
107 def __init__(self
, rwid
, opsubset
=CompLDSTOpSubset
, name
=None):
108 CompUnitRecord
.__init
__(self
, opsubset
, rwid
,
109 n_src
=3, n_dst
=2, name
=name
)
111 self
.ad
= go_record(1, name
="cu_ad") # address go in, req out
112 self
.st
= go_record(1, name
="cu_st") # store go in, req out
114 self
.exc_o
= LDSTException("exc_o")
116 self
.ld_o
= Signal(reset_less
=True) # operation is a LD
117 self
.st_o
= Signal(reset_less
=True) # operation is a ST
119 # hmm... are these necessary?
120 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
121 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
124 class LDSTCompUnit(RegSpecAPI
, Elaboratable
):
125 """LOAD / STORE Computation Unit
130 * :pi: a PortInterface to the memory subsystem (read-write capable)
131 * :rwid: register width
132 * :awid: address width
136 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
140 * :data_o: Dest out (LD) - managed by wr[0] go/req
141 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
142 * :exc_o: Address/Data Exception occurred. LD/ST must terminate
144 TODO: make exc_o a data-type rather than a single-bit signal
150 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
151 * :issue_i: LD/ST is being "issued".
152 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
153 * :go_rd_i: read is being actioned (latches in src regs)
154 * :go_wr_i: write mode (exactly like ALU CompUnit)
155 * :go_ad_i: address is being actioned (triggers actual mem LD)
156 * :go_st_i: store is being actioned (triggers actual mem STORE)
157 * :go_die_i: resets the unit back to "wait for issue"
159 Control Signals (Out)
160 ---------------------
162 * :busy_o: function unit is busy
163 * :rd_rel_o: request src1/src2
164 * :adr_rel_o: request address (from mem)
165 * :sto_rel_o: request store (to mem)
166 * :req_rel_o: request write (result)
167 * :load_mem_o: activate memory LOAD
168 * :stwd_mem_o: activate memory STORE
170 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
171 in a single cycle and the CompUnit set back to doing another op.
172 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
173 depending on whether the operation is a ST or LD.
175 Note: LDSTCompUnit takes care of LE/BE normalisation:
176 * LD data is normalised after receipt from the PortInterface
177 * ST data is normalised *prior* to sending onto the PortInterface
178 TODO: use one module for the byte-reverse as it's quite expensive in gates
181 def __init__(self
, pi
=None, rwid
=64, awid
=48, opsubset
=CompLDSTOpSubset
,
182 debugtest
=False, name
=None):
183 super().__init
__(rwid
)
186 self
.cu
= cu
= LDSTCompUnitRecord(rwid
, opsubset
, name
=name
)
187 self
.debugtest
= debugtest
189 # POWER-compliant LD/ST has index and update: *fixed* number of ports
190 self
.n_src
= n_src
= 3 # RA, RB, RT/RS
191 self
.n_dst
= n_dst
= 2 # RA, RT/RS
193 # set up array of src and dest signals
194 for i
in range(n_src
):
195 j
= i
+ 1 # name numbering to match src1/src2
197 setattr(self
, name
, getattr(cu
, name
))
200 for i
in range(n_dst
):
201 j
= i
+ 1 # name numbering to match dest1/2...
202 name
= "dest%d_o" % j
203 setattr(self
, name
, getattr(cu
, name
))
208 self
.rdmaskn
= cu
.rdmaskn
209 self
.wrmask
= cu
.wrmask
214 # HACK: get data width from dest[0]. this is used across the board
215 # (it really shouldn't be)
216 self
.data_wid
= self
.dest
[0].shape()
218 self
.go_rd_i
= self
.rd
.go_i
# temporary naming
219 self
.go_wr_i
= self
.wr
.go_i
# temporary naming
220 self
.go_ad_i
= self
.ad
.go_i
# temp naming: go address in
221 self
.go_st_i
= self
.st
.go_i
# temp naming: go store in
223 self
.rd_rel_o
= self
.rd
.rel_o
# temporary naming
224 self
.req_rel_o
= self
.wr
.rel_o
# temporary naming
225 self
.adr_rel_o
= self
.ad
.rel_o
# request address (from mem)
226 self
.sto_rel_o
= self
.st
.rel_o
# request store (to mem)
228 self
.issue_i
= cu
.issue_i
229 self
.shadown_i
= cu
.shadown_i
230 self
.go_die_i
= cu
.go_die_i
232 self
.oper_i
= cu
.oper_i
233 self
.src_i
= cu
._src
_i
235 self
.data_o
= Data(self
.data_wid
, name
="o") # Dest1 out: RT
236 self
.addr_o
= Data(self
.data_wid
, name
="ea") # Addr out: Update => RA
237 self
.exc_o
= cu
.exc_o
238 self
.done_o
= cu
.done_o
239 self
.busy_o
= cu
.busy_o
244 self
.load_mem_o
= cu
.load_mem_o
245 self
.stwd_mem_o
= cu
.stwd_mem_o
247 def elaborate(self
, platform
):
253 issue_i
= self
.issue_i
255 #####################
256 # latches for the FSM.
257 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
258 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
259 m
.submodules
.alu_l
= alu_l
= SRLatch(sync
=False, name
="alu")
260 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False, name
="adr")
261 m
.submodules
.lod_l
= lod_l
= SRLatch(sync
=False, name
="lod")
262 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False, name
="sto")
263 m
.submodules
.wri_l
= wri_l
= SRLatch(sync
=False, name
="wri")
264 m
.submodules
.upd_l
= upd_l
= SRLatch(sync
=False, name
="upd")
265 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
266 m
.submodules
.lsd_l
= lsd_l
= SRLatch(sync
=False, name
="lsd") # done
272 op_is_ld
= Signal(reset_less
=True)
273 op_is_st
= Signal(reset_less
=True)
275 # ALU/LD data output control
276 alu_valid
= Signal(reset_less
=True) # ALU operands are valid
277 alu_ok
= Signal(reset_less
=True) # ALU out ok (1 clock delay valid)
278 addr_ok
= Signal(reset_less
=True) # addr ok (from PortInterface)
279 ld_ok
= Signal(reset_less
=True) # LD out ok from PortInterface
280 wr_any
= Signal(reset_less
=True) # any write (incl. store)
281 rda_any
= Signal(reset_less
=True) # any read for address ops
282 rd_done
= Signal(reset_less
=True) # all *necessary* operands read
283 wr_reset
= Signal(reset_less
=True) # final reset condition
286 alu_o
= Signal(self
.data_wid
, reset_less
=True)
287 ldd_o
= Signal(self
.data_wid
, reset_less
=True)
289 ##############################
290 # reset conditions for latches
292 # temporaries (also convenient when debugging)
293 reset_o
= Signal(reset_less
=True) # reset opcode
294 reset_w
= Signal(reset_less
=True) # reset write
295 reset_u
= Signal(reset_less
=True) # reset update
296 reset_a
= Signal(reset_less
=True) # reset adr latch
297 reset_i
= Signal(reset_less
=True) # issue|die (use a lot)
298 reset_r
= Signal(self
.n_src
, reset_less
=True) # reset src
299 reset_s
= Signal(reset_less
=True) # reset store
301 comb
+= reset_i
.eq(issue_i | self
.go_die_i
) # various
302 comb
+= reset_o
.eq(self
.done_o | self
.go_die_i
) # opcode reset
303 comb
+= reset_w
.eq(self
.wr
.go_i
[0] | self
.go_die_i
) # write reg 1
304 comb
+= reset_u
.eq(self
.wr
.go_i
[1] | self
.go_die_i
) # update (reg 2)
305 comb
+= reset_s
.eq(self
.go_st_i | self
.go_die_i
) # store reset
306 comb
+= reset_r
.eq(self
.rd
.go_i |
Repl(self
.go_die_i
, self
.n_src
))
307 comb
+= reset_a
.eq(self
.go_ad_i | self
.go_die_i
)
309 p_st_go
= Signal(reset_less
=True)
310 sync
+= p_st_go
.eq(self
.st
.go_i
)
312 # decode bits of operand (latched)
313 oper_r
= CompLDSTOpSubset(name
="oper_r") # Dest register
314 comb
+= op_is_st
.eq(oper_r
.insn_type
== MicrOp
.OP_STORE
) # ST
315 comb
+= op_is_ld
.eq(oper_r
.insn_type
== MicrOp
.OP_LOAD
) # LD
316 op_is_update
= oper_r
.ldst_mode
== LDSTMode
.update
# UPDATE
317 op_is_cix
= oper_r
.ldst_mode
== LDSTMode
.cix
# cache-inhibit
318 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
319 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
320 comb
+= self
.ld_o
.eq(op_is_ld
)
321 comb
+= self
.st_o
.eq(op_is_st
)
323 ##########################
324 # FSM implemented through sequence of latches. approximately this:
326 # - src_l[0] : operands
328 # - alu_l : looks after add of src1/2/imm (EA)
329 # - adr_l : waits for add (EA)
330 # - upd_l : waits for adr and Regfile (port 2)
332 # - lod_l : waits for adr (EA) and for LD Data
333 # - wri_l : waits for LD Data and Regfile (port 1)
334 # - st_l : waits for alu and operand2
335 # - rst_l : waits for all FSM paths to converge.
336 # NOTE: use sync to stop combinatorial loops.
338 # opcode latch - inverted so that busy resets to 0
339 # note this MUST be sync so as to avoid a combinatorial loop
340 # between busy_o and issue_i on the reset latch (rst_l)
341 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
342 sync
+= opc_l
.r
.eq(reset_o
) # XXX NOTE: INVERTED FROM book!
345 sync
+= src_l
.s
.eq(Repl(issue_i
, self
.n_src
))
346 sync
+= src_l
.r
.eq(reset_r
)
348 # alu latch. use sync-delay between alu_ok and valid to generate pulse
349 comb
+= alu_l
.s
.eq(reset_i
)
350 comb
+= alu_l
.r
.eq(alu_ok
& ~alu_valid
& ~rda_any
)
353 comb
+= adr_l
.s
.eq(reset_i
)
354 sync
+= adr_l
.r
.eq(reset_a
)
357 comb
+= lod_l
.s
.eq(reset_i
)
358 comb
+= lod_l
.r
.eq(ld_ok
)
361 comb
+= wri_l
.s
.eq(issue_i
)
362 sync
+= wri_l
.r
.eq(reset_w |
Repl(wr_reset |
363 (~self
.pi
.busy_o
& op_is_update
),
364 #(self.pi.busy_o & op_is_update),
365 #self.done_o | (self.pi.busy_o & op_is_update),
368 # update-mode operand latch (EA written to reg 2)
369 sync
+= upd_l
.s
.eq(reset_i
)
370 sync
+= upd_l
.r
.eq(reset_u
)
373 comb
+= sto_l
.s
.eq(addr_ok
& op_is_st
)
374 sync
+= sto_l
.r
.eq(reset_s | p_st_go
)
376 # ld/st done. needed to stop LD/ST from activating repeatedly
377 comb
+= lsd_l
.s
.eq(issue_i
)
378 sync
+= lsd_l
.r
.eq(reset_s | p_st_go | ld_ok
)
381 comb
+= rst_l
.s
.eq(addr_ok
) # start when address is ready
382 comb
+= rst_l
.r
.eq(issue_i
)
384 # create a latch/register for the operand
385 with m
.If(self
.issue_i
):
386 sync
+= oper_r
.eq(self
.oper_i
)
387 with m
.If(self
.done_o
):
391 ldd_r
= Signal(self
.data_wid
, reset_less
=True) # Dest register
392 latchregister(m
, ldd_o
, ldd_r
, ld_ok
, name
="ldo_r")
394 # and for each input from the incoming src operands
396 for i
in range(self
.n_src
):
398 src_r
= Signal(self
.data_wid
, name
=name
, reset_less
=True)
399 with m
.If(self
.rd
.go_i
[i
]):
400 sync
+= src_r
.eq(self
.src_i
[i
])
401 with m
.If(self
.issue_i
):
405 # and one for the output from the ADD (for the EA)
406 addr_r
= Signal(self
.data_wid
, reset_less
=True) # Effective Address
407 latchregister(m
, alu_o
, addr_r
, alu_l
.q
, "ea_r")
409 # select either zero or src1 if opcode says so
410 op_is_z
= oper_r
.zero_a
411 src1_or_z
= Signal(self
.data_wid
, reset_less
=True)
412 m
.d
.comb
+= src1_or_z
.eq(Mux(op_is_z
, 0, srl
[0]))
414 # select either immediate or src2 if opcode says so
415 op_is_imm
= oper_r
.imm_data
.ok
416 src2_or_imm
= Signal(self
.data_wid
, reset_less
=True)
417 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.data
, srl
[1]))
419 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
420 comb
+= alu_o
.eq(src1_or_z
+ src2_or_imm
) # actual EA
421 m
.d
.sync
+= alu_ok
.eq(alu_valid
) # keep ack in sync with EA
423 ############################
424 # Control Signal calculation
428 comb
+= self
.busy_o
.eq(opc_l
.q
) # | self.pi.busy_o) # busy out
430 # 1st operand read-request only when zero not active
431 # 2nd operand only needed when immediate is not active
432 slg
= Cat(op_is_z
, op_is_imm
)
433 bro
= Repl(self
.busy_o
, self
.n_src
)
434 comb
+= self
.rd
.rel_o
.eq(src_l
.q
& bro
& ~slg
& ~self
.rdmaskn
)
436 # note when the address-related read "go" signals are active
437 comb
+= rda_any
.eq(self
.rd
.go_i
[0] | self
.rd
.go_i
[1])
439 # alu input valid when 1st and 2nd ops done (or imm not active)
440 comb
+= alu_valid
.eq(busy_o
& ~
(self
.rd
.rel_o
[0] | self
.rd
.rel_o
[1]))
442 # 3rd operand only needed when operation is a store
443 comb
+= self
.rd
.rel_o
[2].eq(src_l
.q
[2] & busy_o
& op_is_st
)
445 # all reads done when alu is valid and 3rd operand needed
446 comb
+= rd_done
.eq(alu_valid
& ~self
.rd
.rel_o
[2])
448 # address release only if addr ready, but Port must be idle
449 comb
+= self
.adr_rel_o
.eq(alu_valid
& adr_l
.q
& busy_o
)
451 # the write/store (etc) all must be cancelled if an exception occurs
452 cancel
= Signal(reset_less
=True)
453 comb
+= cancel
.eq(self
.exc_o
.happened | self
.shadown_i
)
455 # store release when st ready *and* all operands read (and no shadow)
456 comb
+= self
.st
.rel_o
.eq(sto_l
.q
& busy_o
& rd_done
& op_is_st
&
459 # request write of LD result. waits until shadow is dropped.
460 comb
+= self
.wr
.rel_o
[0].eq(rd_done
& wri_l
.q
& busy_o
& lod_l
.qn
&
463 # request write of EA result only in update mode
464 comb
+= self
.wr
.rel_o
[1].eq(upd_l
.q
& busy_o
& op_is_update
&
467 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
468 comb
+= wr_any
.eq(self
.st
.go_i | p_st_go |
469 self
.wr
.go_i
[0] | self
.wr
.go_i
[1])
470 comb
+= wr_reset
.eq(rst_l
.q
& busy_o
& cancel
&
471 ~
(self
.st
.rel_o | self
.wr
.rel_o
[0] |
473 (lod_l
.qn | op_is_st
)
475 comb
+= self
.done_o
.eq(wr_reset
& (~self
.pi
.busy_o | op_is_ld
))
477 ######################
478 # Data/Address outputs
480 # put the LD-output register directly onto the output bus on a go_write
481 comb
+= self
.data_o
.data
.eq(self
.dest
[0])
482 with m
.If(self
.wr
.go_i
[0]):
483 comb
+= self
.dest
[0].eq(ldd_r
)
485 # "update" mode, put address out on 2nd go-write
486 comb
+= self
.addr_o
.data
.eq(self
.dest
[1])
487 with m
.If(op_is_update
& self
.wr
.go_i
[1]):
488 comb
+= self
.dest
[1].eq(addr_r
)
490 # need to look like MultiCompUnit: put wrmask out.
491 # XXX may need to make this enable only when write active
492 comb
+= self
.wrmask
.eq(bro
& Cat(op_is_ld
, op_is_update
))
494 ###########################
495 # PortInterface connections
498 # connect to LD/ST PortInterface.
499 comb
+= pi
.is_ld_i
.eq(op_is_ld
& busy_o
) # decoded-LD
500 comb
+= pi
.is_st_i
.eq(op_is_st
& busy_o
) # decoded-ST
501 comb
+= pi
.data_len
.eq(oper_r
.data_len
) # data_len
502 # address: use sync to avoid long latency
503 sync
+= pi
.addr
.data
.eq(addr_r
) # EA from adder
504 sync
+= pi
.addr
.ok
.eq(alu_ok
& lsd_l
.q
) # "do address stuff" (once)
505 comb
+= self
.exc_o
.eq(pi
.exc_o
) # exception occurred
506 comb
+= addr_ok
.eq(self
.pi
.addr_ok_o
) # no exc, address fine
507 # connect MSR.PR for priv/virt operation
508 comb
+= pi
.msr_pr
.eq(oper_r
.msr
[MSR
.PR
])
511 revnorev
= Signal(64, reset_less
=True)
512 with m
.If(oper_r
.byte_reverse
):
513 # byte-reverse the data based on ld/st width (turn it to LE)
514 data_len
= oper_r
.data_len
515 lddata_r
= byte_reverse(m
, 'lddata_r', pi
.ld
.data
, data_len
)
516 comb
+= revnorev
.eq(lddata_r
) # put reversed- data out
518 comb
+= revnorev
.eq(pi
.ld
.data
) # put data out, straight (as BE)
520 # then check sign-extend
521 with m
.If(oper_r
.sign_extend
):
522 # okok really should "if data_len == 4" and so on here
523 with m
.If(oper_r
.data_len
== 2):
524 comb
+= ldd_o
.eq(exts(revnorev
, 16, 64)) # sign-extend hword
526 comb
+= ldd_o
.eq(exts(revnorev
, 32, 64)) # sign-extend dword
528 comb
+= ldd_o
.eq(revnorev
)
530 # ld - ld gets latched in via lod_l
531 comb
+= ld_ok
.eq(pi
.ld
.ok
) # ld.ok *closes* (freezes) ld data
534 op3
= srl
[2] # 3rd operand latch
535 with m
.If(oper_r
.byte_reverse
):
536 # byte-reverse the data based on width
537 data_len
= oper_r
.data_len
538 stdata_r
= byte_reverse(m
, 'stdata_r', op3
, data_len
)
539 comb
+= pi
.st
.data
.eq(stdata_r
)
541 comb
+= pi
.st
.data
.eq(op3
)
542 # store - data goes in based on go_st
543 comb
+= pi
.st
.ok
.eq(self
.st
.go_i
) # go store signals st data valid
547 def get_out(self
, i
):
548 """make LDSTCompUnit look like RegSpecALUAPI. these correspond
549 to LDSTOutputData o and o1 respectively.
552 return self
.data_o
# LDSTOutputData.regspec o
554 return self
.addr_o
# LDSTOutputData.regspec o1
555 # return self.dest[i]
557 def get_fu_out(self
, i
):
558 return self
.get_out(i
)
568 yield from self
.oper_i
.ports()
569 yield from self
.src_i
575 yield from self
.data_o
.ports()
576 yield from self
.addr_o
.ports()
577 yield self
.load_mem_o
578 yield self
.stwd_mem_o
584 def wait_for(sig
, wait
=True, test1st
=False):
586 print("wait for", sig
, v
, wait
, test1st
)
587 if test1st
and bool(v
) == wait
:
592 #print("...wait for", sig, v)
597 def store(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False,
599 print("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
600 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_STORE
)
601 yield dut
.oper_i
.data_len
.eq(2) # half-word
602 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
603 yield dut
.src1_i
.eq(src1
)
604 yield dut
.src2_i
.eq(src2
)
605 yield dut
.src3_i
.eq(src3
)
606 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
607 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
608 yield dut
.oper_i
.update
.eq(update
)
609 yield dut
.issue_i
.eq(1)
611 yield dut
.issue_i
.eq(0)
617 # wait for all active rel signals to come up
619 rel
= yield dut
.rd
.rel_o
620 if rel
== active_rel
:
623 yield dut
.rd
.go
.eq(active_rel
)
625 yield dut
.rd
.go
.eq(0)
627 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
628 # yield from wait_for(dut.adr_rel_o)
629 # yield dut.ad.go.eq(1)
631 # yield dut.ad.go.eq(0)
634 yield from wait_for(dut
.wr
.rel_o
[1])
635 yield dut
.wr
.go
.eq(0b10)
637 addr
= yield dut
.addr_o
639 yield dut
.wr
.go
.eq(0)
643 yield from wait_for(dut
.sto_rel_o
)
644 yield dut
.go_st_i
.eq(1)
646 yield dut
.go_st_i
.eq(0)
647 yield from wait_for(dut
.busy_o
, False)
648 # wait_for(dut.stwd_mem_o)
653 def load(dut
, src1
, src2
, imm
, imm_ok
=True, update
=False, zero_a
=False,
655 print("LD", src1
, src2
, imm
, imm_ok
, update
)
656 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_LOAD
)
657 yield dut
.oper_i
.data_len
.eq(2) # half-word
658 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
659 yield dut
.src1_i
.eq(src1
)
660 yield dut
.src2_i
.eq(src2
)
661 yield dut
.oper_i
.zero_a
.eq(zero_a
)
662 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
663 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
664 yield dut
.issue_i
.eq(1)
666 yield dut
.issue_i
.eq(0)
669 # set up read-operand flags
671 if not imm_ok
: # no immediate means RB register needs to be read
673 if not zero_a
: # no zero-a means RA needs to be read
676 # wait for the operands (RA, RB, or both)
678 yield dut
.rd
.go
.eq(rd
)
679 yield from wait_for(dut
.rd
.rel_o
)
680 yield dut
.rd
.go
.eq(0)
682 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
683 # yield dut.ad.go.eq(1)
685 # yield dut.ad.go.eq(0)
688 yield from wait_for(dut
.wr
.rel_o
[1])
689 yield dut
.wr
.go
.eq(0b10)
691 addr
= yield dut
.addr_o
693 yield dut
.wr
.go
.eq(0)
697 yield from wait_for(dut
.wr
.rel_o
[0], test1st
=True)
698 yield dut
.wr
.go
.eq(1)
700 data
= yield dut
.data_o
702 yield dut
.wr
.go
.eq(0)
703 yield from wait_for(dut
.busy_o
)
705 # wait_for(dut.stwd_mem_o)
714 # two STs (different addresses)
715 yield from store(dut
, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
716 yield from store(dut
, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
718 # two LDs (deliberately LD from the 1st address then 2nd)
719 data
, addr
= yield from load(dut
, 4, 0, 2)
720 assert data
== 0x0003, "returned %x" % data
721 data
, addr
= yield from load(dut
, 2, 0, 2)
722 assert data
== 0x0009, "returned %x" % data
726 yield from store(dut
, 9, 5, 3, 0, imm_ok
=False)
727 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False)
728 assert data
== 0x0003, "returned %x" % data
730 # update-immediate version
731 addr
= yield from store(dut
, 9, 6, 3, 2, update
=True)
732 assert addr
== 0x000b, "returned %x" % addr
734 # update-indexed version
735 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False, update
=True)
736 assert data
== 0x0003, "returned %x" % data
737 assert addr
== 0x000e, "returned %x" % addr
739 # immediate *and* zero version
740 data
, addr
= yield from load(dut
, 1, 4, 8, imm_ok
=True, zero_a
=True)
741 assert data
== 0x0008, "returned %x" % data
744 class TestLDSTCompUnit(LDSTCompUnit
):
746 def __init__(self
, rwid
):
747 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
748 self
.l0
= l0
= TstL0CacheBuffer()
749 pi
= l0
.l0
.dports
[0].pi
750 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
752 def elaborate(self
, platform
):
753 m
= LDSTCompUnit
.elaborate(self
, platform
)
754 m
.submodules
.l0
= self
.l0
755 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
759 def test_scoreboard():
761 dut
= TestLDSTCompUnit(16)
762 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
763 with
open("test_ldst_comp.il", "w") as f
:
766 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
769 class TestLDSTCompUnitRegSpec(LDSTCompUnit
):
772 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
773 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
774 regspec
= LDSTPipeSpec
.regspec
775 self
.l0
= l0
= TstL0CacheBuffer()
776 pi
= l0
.l0
.dports
[0].pi
777 LDSTCompUnit
.__init
__(self
, pi
, regspec
, 4)
779 def elaborate(self
, platform
):
780 m
= LDSTCompUnit
.elaborate(self
, platform
)
781 m
.submodules
.l0
= self
.l0
782 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
786 def test_scoreboard_regspec():
788 dut
= TestLDSTCompUnitRegSpec()
789 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
790 with
open("test_ldst_comp.il", "w") as f
:
793 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_regspec.vcd')
796 if __name__
== '__main__':
797 test_scoreboard_regspec()