3 based on Anton Blanchard microwatt dcache.vhdl
7 from enum
import Enum
, unique
9 from nmigen
import Module
, Signal
, Elaboratable
,
11 from nmigen
.cli
import main
12 from nmigen
.iocontrol
import RecordObject
13 from nmigen
.util
import log2_int
15 from experiment
.mem_types
import LoadStore1ToDcacheType
,
16 DcacheToLoadStore1Type
,
20 from experiment
.wb_types
import WB_ADDR_BITS
, WB_DATA_BITS
, WB_SEL_BITS
,
21 WBAddrType
, WBDataType
, WBSelType
,
22 WbMasterOut
, WBSlaveOut
, WBMasterOutVector
,
23 WBSlaveOutVector
, WBIOMasterOut
,
27 # -- Set associative dcache write-through
29 # -- TODO (in no specific order):
31 # -- * See list in icache.vhdl
32 # -- * Complete load misses on the cycle when WB data comes instead of
33 # -- at the end of line (this requires dealing with requests coming in
34 # -- while not idle...)
37 # use ieee.std_logic_1164.all;
38 # use ieee.numeric_std.all;
42 # use work.common.all;
43 # use work.helpers.all;
44 # use work.wishbone_types.all;
47 class Dcache(Elaboratable
):
49 # -- Line size in bytes
50 # LINE_SIZE : positive := 64;
51 # -- Number of lines in a set
52 # NUM_LINES : positive := 32;
54 # NUM_WAYS : positive := 4;
55 # -- L1 DTLB entries per set
56 # TLB_SET_SIZE : positive := 64;
57 # -- L1 DTLB number of sets
58 # TLB_NUM_WAYS : positive := 2;
59 # -- L1 DTLB log_2(page_size)
60 # TLB_LG_PGSZ : positive := 12;
61 # -- Non-zero to enable log data collection
62 # LOG_LENGTH : natural := 0
67 # Number of lines in a set
71 # L1 DTLB entries per set
72 self
.TLB_SET_SIZE
= 64
73 # L1 DTLB number of sets
75 # L1 DTLB log_2(page_size)
77 # Non-zero to enable log data collection
80 # clk : in std_ulogic;
81 # rst : in std_ulogic;
83 # d_in : in Loadstore1ToDcacheType;
84 # d_out : out DcacheToLoadstore1Type;
86 # m_in : in MmuToDcacheType;
87 # m_out : out DcacheToMmuType;
89 # stall_out : out std_ulogic;
91 # wishbone_out : out wishbone_master_out;
92 # wishbone_in : in wishbone_slave_out;
94 # log_out : out std_ulogic_vector(19 downto 0)
96 self
.d_in
= LoadStore1ToDcacheType()
97 self
.d_out
= DcacheToLoadStore1Type()
99 self
.m_in
= MmuToDcacheType()
100 self
.m_out
= DcacheToMmuType()
102 self
.stall_out
= Signal()
104 self
.wb_out
= WBMasterOut()
105 self
.wb_in
= WBSlaveOut()
107 self
.log_out
= Signal(20)
110 # architecture rtl of dcache is
111 def elaborate(self
, platform
):
112 LINE_SIZE
= self
.LINE_SIZE
113 NUM_LINES
= self
.NUM_LINES
114 NUM_WAYS
= self
.NUM_WAYS
115 TLB_SET_SIZE
= self
.TLB_SET_SIZE
116 TLB_NUM_WAYS
= self
.TLB_NUM_WAYS
117 TLB_LG_PGSZ
= self
.TLB_LG_PGSZ
118 LOG_LENGTH
= self
.LOG_LENGTH
120 # -- BRAM organisation: We never access more than
121 # -- wishbone_data_bits at a time so to save
122 # -- resources we make the array only that wide, and
123 # -- use consecutive indices for to make a cache "line"
125 # -- ROW_SIZE is the width in bytes of the BRAM
126 # -- (based on WB, so 64-bits)
127 # constant ROW_SIZE : natural := wishbone_data_bits / 8;
128 # BRAM organisation: We never access more than
129 # -- wishbone_data_bits at a time so to save
130 # -- resources we make the array only that wide, and
131 # -- use consecutive indices for to make a cache "line"
133 # -- ROW_SIZE is the width in bytes of the BRAM
134 # -- (based on WB, so 64-bits)
135 ROW_SIZE
= WB_DATA_BITS
/ 8;
137 # -- ROW_PER_LINE is the number of row (wishbone
138 # -- transactions) in a line
139 # constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
140 # -- BRAM_ROWS is the number of rows in BRAM needed
141 # -- to represent the full dcache
142 # constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
143 # ROW_PER_LINE is the number of row (wishbone
144 # transactions) in a line
145 ROW_PER_LINE
= LINE_SIZE
/ ROW_SIZE
146 # BRAM_ROWS is the number of rows in BRAM needed
147 # to represent the full dcache
148 BRAM_ROWS
= NUM_LINES
* ROW_PER_LINE
150 # -- Bit fields counts in the address
152 # -- REAL_ADDR_BITS is the number of real address
153 # -- bits that we store
154 # constant REAL_ADDR_BITS : positive := 56;
155 # -- ROW_BITS is the number of bits to select a row
156 # constant ROW_BITS : natural := log2(BRAM_ROWS);
157 # -- ROW_LINEBITS is the number of bits to select
158 # -- a row within a line
159 # constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
160 # -- LINE_OFF_BITS is the number of bits for
161 # -- the offset in a cache line
162 # constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
163 # -- ROW_OFF_BITS is the number of bits for
164 # -- the offset in a row
165 # constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
166 # -- INDEX_BITS is the number if bits to
167 # -- select a cache line
168 # constant INDEX_BITS : natural := log2(NUM_LINES);
169 # -- SET_SIZE_BITS is the log base 2 of the set size
170 # constant SET_SIZE_BITS : natural := LINE_OFF_BITS
172 # -- TAG_BITS is the number of bits of
173 # -- the tag part of the address
174 # constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
175 # -- TAG_WIDTH is the width in bits of each way of the tag RAM
176 # constant TAG_WIDTH : natural := TAG_BITS + 7
177 # - ((TAG_BITS + 7) mod 8);
178 # -- WAY_BITS is the number of bits to select a way
179 # constant WAY_BITS : natural := log2(NUM_WAYS);
180 # Bit fields counts in the address
182 # REAL_ADDR_BITS is the number of real address
185 # ROW_BITS is the number of bits to select a row
186 ROW_BITS
= log2_int(BRAM_ROWS
)
187 # ROW_LINE_BITS is the number of bits to select
188 # a row within a line
189 ROW_LINE_BITS
= log2_int(ROW_PER_LINE
)
190 # LINE_OFF_BITS is the number of bits for
191 # the offset in a cache line
192 LINE_OFF_BITS
= log2_int(LINE_SIZE
)
193 # ROW_OFF_BITS is the number of bits for
194 # the offset in a row
195 ROW_OFF_BITS
= log2_int(ROW_SIZE
)
196 # INDEX_BITS is the number if bits to
197 # select a cache line
198 INDEX_BITS
= log2_int(NUM_LINES
)
199 # SET_SIZE_BITS is the log base 2 of the set size
200 SET_SIZE_BITS
= LINE_OFF_BITS
+ INDEX_BITS
201 # TAG_BITS is the number of bits of
202 # the tag part of the address
203 TAG_BITS
= REAL_ADDR_BITS
- SET_SIZE_BITS
204 # TAG_WIDTH is the width in bits of each way of the tag RAM
205 TAG_WIDTH
= TAG_BITS
+ 7 - ((TAG_BITS
+ 7) % 8)
206 # WAY_BITS is the number of bits to select a way
207 WAY_BITS
= log2_int(NUM_WAYS
)
209 # -- Example of layout for 32 lines of 64 bytes:
211 # -- .. tag |index| line |
213 # -- .. | |---| | ROW_LINEBITS (3)
214 # -- .. | |--- - --| LINE_OFF_BITS (6)
215 # -- .. | |- --| ROW_OFF_BITS (3)
216 # -- .. |----- ---| | ROW_BITS (8)
217 # -- .. |-----| | INDEX_BITS (5)
218 # -- .. --------| | TAG_BITS (45)
219 # Example of layout for 32 lines of 64 bytes:
221 # .. tag |index| line |
223 # .. | |---| | ROW_LINE_BITS (3)
224 # .. | |--- - --| LINE_OFF_BITS (6)
225 # .. | |- --| ROW_OFF_BITS (3)
226 # .. |----- ---| | ROW_BITS (8)
227 # .. |-----| | INDEX_BITS (5)
228 # .. --------| | TAG_BITS (45)
231 # subtype row_t is integer range 0 to BRAM_ROWS-1;
232 # subtype index_t is integer range 0 to NUM_LINES-1;
233 # subtype way_t is integer range 0 to NUM_WAYS-1;
234 # subtype row_in_line_t is unsigned(ROW_LINE_BITS-1 downto 0);
238 ROW_IN_LINE
= ROW_LINE_BITS
240 # -- The cache data BRAM organized as described above for each way
241 # subtype cache_row_t is
242 # std_ulogic_vector(wishbone_data_bits-1 downto 0);
243 # The cache data BRAM organized as described above for each way
244 CACHE_ROW
= WB_DATA_BITS
246 # -- The cache tags LUTRAM has a row per set.
247 # -- Vivado is a pain and will not handle a
248 # -- clean (commented) definition of the cache
249 # -- tags as a 3d memory. For now, work around
250 # -- it by putting all the tags
251 # subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
252 # The cache tags LUTRAM has a row per set.
253 # Vivado is a pain and will not handle a
254 # clean (commented) definition of the cache
255 # tags as a 3d memory. For now, work around
256 # it by putting all the tags
259 # -- type cache_tags_set_t is array(way_t) of cache_tag_t;
260 # -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
261 # constant TAG_RAM_WIDTH : natural := TAG_WIDTH * NUM_WAYS;
262 # subtype cache_tags_set_t is
263 # std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
264 # type cache_tags_array_t is array(index_t) of cache_tags_set_t;
265 # type cache_tags_set_t is array(way_t) of cache_tag_t;
266 # type cache_tags_array_t is array(index_t) of cache_tags_set_t;
267 TAG_RAM_WIDTH
= TAG_WIDTH
* NUM_WAYS
269 CACHE_TAG_SET
= TAG_RAM_WIDTH
272 return Array(CacheTagSet() for x
in range(INDEX
))
274 # -- The cache valid bits
275 # subtype cache_way_valids_t is
276 # std_ulogic_vector(NUM_WAYS-1 downto 0);
277 # type cache_valids_t is array(index_t) of cache_way_valids_t;
278 # type row_per_line_valid_t is
279 # array(0 to ROW_PER_LINE - 1) of std_ulogic;
280 # The cache valid bits
281 CACHE_WAY_VALID_BITS
= NUM_WAYS
283 def CacheValidBitsArray():
284 return Array(CacheWayValidBits() for x
in range(INDEX
))
286 def RowPerLineValidArray():
287 return Array(Signal() for x
in range(ROW_PER_LINE
))
289 # -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
290 # signal cache_tags : cache_tags_array_t;
291 # signal cache_tag_set : cache_tags_set_t;
292 # signal cache_valids : cache_valids_t;
294 # attribute ram_style : string;
295 # attribute ram_style of cache_tags : signal is "distributed";
296 # Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
297 cache_tags
= CacheTagArray()
298 cache_tag_set
= Signal(CACHE_TAG_SET
)
299 cache_valid_bits
= CacheValidBitsArray()
301 # TODO attribute ram_style : string;
302 # TODO attribute ram_style of cache_tags : signal is "distributed";
305 # constant TLB_SET_BITS : natural := log2(TLB_SET_SIZE);
306 # constant TLB_WAY_BITS : natural := log2(TLB_NUM_WAYS);
307 # constant TLB_EA_TAG_BITS : natural :=
308 # 64 - (TLB_LG_PGSZ + TLB_SET_BITS);
309 # constant TLB_TAG_WAY_BITS : natural :=
310 # TLB_NUM_WAYS * TLB_EA_TAG_BITS;
311 # constant TLB_PTE_BITS : natural := 64;
312 # constant TLB_PTE_WAY_BITS : natural :=
313 # TLB_NUM_WAYS * TLB_PTE_BITS;
315 TLB_SET_BITS
= log2_int(TLB_SET_SIZE
)
316 TLB_WAY_BITS
= log2_int(TLB_NUM_WAYS
)
317 TLB_EA_TAG_BITS
= 64 - (TLB_LG_PGSZ
+ TLB_SET_BITS
)
318 TLB_TAG_WAY_BITS
= TLB_NUM_WAYS
* TLB_EA_TAG_BITS
320 TLB_PTE_WAY_BITS
= TLB_NUM_WAYS
* TLB_PTE_BITS
;
322 # subtype tlb_way_t is integer range 0 to TLB_NUM_WAYS - 1;
323 # subtype tlb_index_t is integer range 0 to TLB_SET_SIZE - 1;
324 # subtype tlb_way_valids_t is
325 # std_ulogic_vector(TLB_NUM_WAYS-1 downto 0);
326 # type tlb_valids_t is
327 # array(tlb_index_t) of tlb_way_valids_t;
328 # subtype tlb_tag_t is
329 # std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
330 # subtype tlb_way_tags_t is
331 # std_ulogic_vector(TLB_TAG_WAY_BITS-1 downto 0);
333 # array(tlb_index_t) of tlb_way_tags_t;
334 # subtype tlb_pte_t is
335 # std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
336 # subtype tlb_way_ptes_t is
337 # std_ulogic_vector(TLB_PTE_WAY_BITS-1 downto 0);
338 # type tlb_ptes_t is array(tlb_index_t) of tlb_way_ptes_t;
339 # type hit_way_set_t is array(tlb_way_t) of way_t;
340 TLB_WAY
= TLB_NUM_WAYS
342 TLB_INDEX
= TLB_SET_SIZE
344 TLB_WAY_VALID_BITS
= TLB_NUM_WAYS
346 def TLBValidBitsArray():
348 Signal(TLB_WAY_VALID_BITS
) for x
in range(TLB_SET_SIZE
)
351 TLB_TAG
= TLB_EA_TAG_BITS
353 TLB_WAY_TAGS
= TLB_TAG_WAY_BITS
357 Signal(TLB_WAY_TAGS
) for x
in range (TLB_SET_SIZE
)
360 TLB_PTE
= TLB_PTE_BITS
362 TLB_WAY_PTES
= TLB_PTE_WAY_BITS
366 Signal(TLB_WAY_PTES
) for x
in range(TLB_SET_SIZE
)
370 return Array(Signal(WAY
) for x
in range(TLB_NUM_WAYS
))
372 # signal dtlb_valids : tlb_valids_t;
373 # signal dtlb_tags : tlb_tags_t;
374 # signal dtlb_ptes : tlb_ptes_t;
376 """note: these are passed to nmigen.hdl.Memory as "attributes". don't
377 know how, just that they are.
379 # attribute ram_style of dtlb_tags : signal is "distributed";
380 # attribute ram_style of dtlb_ptes : signal is "distributed";
381 dtlb_valids
= TLBValidBitsArray()
382 dtlb_tags
= TLBTagsArray()
383 dtlb_ptes
= TLBPtesArray()
384 # TODO attribute ram_style of dtlb_tags : signal is "distributed";
385 # TODO attribute ram_style of dtlb_ptes : signal is "distributed";
388 # -- Record for storing permission, attribute, etc. bits from a PTE
389 # type perm_attr_t is record
390 # reference : std_ulogic;
391 # changed : std_ulogic;
392 # nocache : std_ulogic;
394 # rd_perm : std_ulogic;
395 # wr_perm : std_ulogic;
397 # Record for storing permission, attribute, etc. bits from a PTE
398 class PermAttr(RecordObject
):
401 self
.reference
= Signal()
402 self
.changed
= Signal()
403 self
.nocache
= Signal()
405 self
.rd_perm
= Signal()
406 self
.wr_perm
= Signal()
408 # function extract_perm_attr(
409 # pte : std_ulogic_vector(TLB_PTE_BITS - 1 downto 0))
410 # return perm_attr_t is
411 # variable pa : perm_attr_t;
413 # pa.reference := pte(8);
414 # pa.changed := pte(7);
415 # pa.nocache := pte(5);
417 # pa.rd_perm := pte(2);
418 # pa.wr_perm := pte(1);
421 def extract_perm_attr(pte
=Signal(TLB_PTE_BITS
)):
423 pa
.reference
= pte
[8]
431 # constant real_mode_perm_attr : perm_attr_t :=
432 # (nocache => '0', others => '1');
433 REAL_MODE_PERM_ATTR
= PermAttr()
434 REAL_MODE_PERM_ATTR
.reference
= 1
435 REAL_MODE_PERM_ATTR
.changed
= 1
436 REAL_MODE_PERM_ATTR
.priv
= 1
437 REAL_MODE_PERM_ATTR
.rd_perm
= 1
438 REAL_MODE_PERM_ATTR
.wr_perm
= 1
440 # -- Type of operation on a "valid" input
444 # OP_BAD, -- NC cache hit, TLB miss, prot/RC failure
445 # OP_STCX_FAIL, -- conditional store w/o reservation
446 # OP_LOAD_HIT, -- Cache hit on load
447 # OP_LOAD_MISS, -- Load missing cache
448 # OP_LOAD_NC, -- Non-cachable load
449 # OP_STORE_HIT, -- Store hitting cache
450 # OP_STORE_MISS -- Store missing cache
452 # Type of operation on a "valid" input
456 OP_BAD
= 1 # NC cache hit, TLB miss, prot/RC failure
457 OP_STCX_FAIL
= 2 # conditional store w/o reservation
458 OP_LOAD_HIT
= 3 # Cache hit on load
459 OP_LOAD_MISS
= 4 # Load missing cache
460 OP_LOAD_NC
= 5 # Non-cachable load
461 OP_STORE_HIT
= 6 # Store hitting cache
462 OP_STORE_MISS
= 7 # Store missing cache
464 # -- Cache state machine
467 # IDLE, -- Normal load hit processing
468 # RELOAD_WAIT_ACK, -- Cache reload wait ack
469 # STORE_WAIT_ACK, -- Store wait ack
470 # NC_LOAD_WAIT_ACK -- Non-cachable load wait ack
472 # Cache state machine
475 IDLE
= 0 # Normal load hit processing
476 RELOAD_WAIT_ACK
= 1 # Cache reload wait ack
477 STORE_WAIT_ACK
= 2 # Store wait ack
478 NC_LOAD_WAIT_ACK
= 3 # Non-cachable load wait ack
480 # -- Dcache operations:
482 # -- In order to make timing, we use the BRAMs with
483 # -- an output buffer, which means that the BRAM
484 # -- output is delayed by an extra cycle.
486 # -- Thus, the dcache has a 2-stage internal pipeline
487 # -- for cache hits with no stalls.
489 # -- All other operations are handled via stalling
490 # -- in the first stage.
492 # -- The second stage can thus complete a hit at the same
493 # -- time as the first stage emits a stall for a complex op.
495 # -- Stage 0 register, basically contains just the latched request
496 # type reg_stage_0_t is record
497 # req : Loadstore1ToDcacheType;
498 # tlbie : std_ulogic;
499 # doall : std_ulogic;
500 # tlbld : std_ulogic;
501 # mmu_req : std_ulogic; -- indicates source of request
505 # In order to make timing, we use the BRAMs with
506 # an output buffer, which means that the BRAM
507 # output is delayed by an extra cycle.
509 # Thus, the dcache has a 2-stage internal pipeline
510 # for cache hits with no stalls.
512 # All other operations are handled via stalling
513 # in the first stage.
515 # The second stage can thus complete a hit at the same
516 # time as the first stage emits a stall for a complex op.
518 # Stage 0 register, basically contains just the latched request
519 class RegStage0(RecordObject
):
522 self
.req
= LoadStore1ToDcacheType()
523 self
.tlbie
= Signal()
524 self
.doall
= Signal()
525 self
.tlbld
= Signal()
526 self
.mmu_req
= Signal() # indicates source of request
528 # signal r0 : reg_stage_0_t;
529 # signal r0_full : std_ulogic;
533 # type mem_access_request_t is record
535 # valid : std_ulogic;
537 # real_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
538 # data : std_ulogic_vector(63 downto 0);
539 # byte_sel : std_ulogic_vector(7 downto 0);
541 # same_tag : std_ulogic;
542 # mmu_req : std_ulogic;
544 class MemAccessRequest(RecordObject
):
548 self
.valid
= Signal()
550 self
.real_addr
= Signal(REAL_ADDR_BITS
)
551 self
.data
= Signal(64)
552 self
.byte_sel
= Signal(8)
553 self
.hit_way
= Signal(WAY
)
554 self
.same_tag
= Signal()
555 self
.mmu_req
= Signal()
557 # -- First stage register, contains state for stage 1 of load hits
558 # -- and for the state machine used by all other operations
559 # type reg_stage_1_t is record
560 # -- Info about the request
561 # full : std_ulogic; -- have uncompleted request
562 # mmu_req : std_ulogic; -- request is from MMU
563 # req : mem_access_request_t;
567 # hit_load_valid : std_ulogic;
568 # hit_index : index_t;
569 # cache_hit : std_ulogic;
572 # tlb_hit : std_ulogic;
573 # tlb_hit_way : tlb_way_t;
574 # tlb_hit_index : tlb_index_t;
576 # -- 2-stage data buffer for data forwarded from writes to reads
577 # forward_data1 : std_ulogic_vector(63 downto 0);
578 # forward_data2 : std_ulogic_vector(63 downto 0);
579 # forward_sel1 : std_ulogic_vector(7 downto 0);
580 # forward_valid1 : std_ulogic;
581 # forward_way1 : way_t;
582 # forward_row1 : row_t;
583 # use_forward1 : std_ulogic;
584 # forward_sel : std_ulogic_vector(7 downto 0);
586 # -- Cache miss state (reload state machine)
589 # write_bram : std_ulogic;
590 # write_tag : std_ulogic;
591 # slow_valid : std_ulogic;
592 # wb : wishbone_master_out;
593 # reload_tag : cache_tag_t;
596 # store_index : index_t;
597 # end_row_ix : row_in_line_t;
598 # rows_valid : row_per_line_valid_t;
599 # acks_pending : unsigned(2 downto 0);
600 # inc_acks : std_ulogic;
601 # dec_acks : std_ulogic;
603 # -- Signals to complete (possibly with error)
604 # ls_valid : std_ulogic;
605 # ls_error : std_ulogic;
606 # mmu_done : std_ulogic;
607 # mmu_error : std_ulogic;
608 # cache_paradox : std_ulogic;
610 # -- Signal to complete a failed stcx.
611 # stcx_fail : std_ulogic;
613 # First stage register, contains state for stage 1 of load hits
614 # and for the state machine used by all other operations
615 class RegStage1(RecordObject
):
618 # Info about the request
619 self
.full
= Signal() # have uncompleted request
620 self
.mmu_req
= Signal() # request is from MMU
621 self
.req
= MemAccessRequest()
624 self
.hit_way
= Signal(WAY
)
625 self
.hit_load_valid
= Signal()
626 self
.hit_index
= Signal(INDEX
)
627 self
.cache_hit
= Signal()
630 self
.tlb_hit
= Signal()
631 self
.tlb_hit_way
= Signal(TLB_WAY
)
632 self
.tlb_hit_index
= Signal(TLB_SET_SIZE
)
634 # 2-stage data buffer for data forwarded from writes to reads
635 self
.forward_data1
= Signal(64)
636 self
.forward_data2
= Signal(64)
637 self
.forward_sel1
= Signal(8)
638 self
.forward_valid1
= Signal()
639 self
.forward_way1
= Signal(WAY
)
640 self
.forward_row1
= Signal(ROW
)
641 self
.use_forward1
= Signal()
642 self
.forward_sel
= Signal(8)
644 # Cache miss state (reload state machine)
647 self
.write_bram
= Signal()
648 self
.write_tag
= Signal()
649 self
.slow_valid
= Signal()
650 self
.wb
= WishboneMasterOut()
651 self
.reload_tag
= Signal(CACHE_TAG
)
652 self
.store_way
= Signal(WAY
)
653 self
.store_row
= Signal(ROW
)
654 self
.store_index
= Signal(INDEX
)
655 self
.end_row_ix
= Signal(ROW_IN_LINE
)
656 self
.rows_valid
= RowPerLineValidArray()
657 self
.acks_pending
= Signal(3)
658 self
.inc_acks
= Signal()
659 self
.dec_acks
= Signal()
661 # Signals to complete (possibly with error)
662 self
.ls_valid
= Signal()
663 self
.ls_error
= Signal()
664 self
.mmu_done
= Signal()
665 self
.mmu_error
= Signal()
666 self
.cache_paradox
= Signal()
668 # Signal to complete a failed stcx.
669 self
.stcx_fail
= Signal()
671 # signal r1 : reg_stage_1_t;
674 # -- Reservation information
676 # type reservation_t is record
677 # valid : std_ulogic;
678 # addr : std_ulogic_vector(63 downto LINE_OFF_BITS);
680 # Reservation information
682 class Reservation(RecordObject
):
686 # TODO LINE_OFF_BITS is 6
687 addr
= Signal(63 downto LINE_OFF_BITS
)
689 # signal reservation : reservation_t;
690 reservation
= Reservation()
692 # -- Async signals on incoming request
693 # signal req_index : index_t;
694 # signal req_row : row_t;
695 # signal req_hit_way : way_t;
696 # signal req_tag : cache_tag_t;
697 # signal req_op : op_t;
698 # signal req_data : std_ulogic_vector(63 downto 0);
699 # signal req_same_tag : std_ulogic;
700 # signal req_go : std_ulogic;
701 # Async signals on incoming request
702 req_index
= Signal(INDEX
)
703 req_row
= Signal(ROW
)
704 req_hit_way
= Signal(WAY
)
705 req_tag
= Signal(CACHE_TAG
)
707 req_data
= Signal(64)
708 req_same_tag
= Signal()
711 # signal early_req_row : row_t;
713 # signal cancel_store : std_ulogic;
714 # signal set_rsrv : std_ulogic;
715 # signal clear_rsrv : std_ulogic;
717 # signal r0_valid : std_ulogic;
718 # signal r0_stall : std_ulogic;
720 # signal use_forward1_next : std_ulogic;
721 # signal use_forward2_next : std_ulogic;
722 early_req_row
= Signal(ROW
)
724 cancel_store
= Signal()
726 clear_rsrv
= Signal()
731 use_forward1_next
= Signal()
732 use_forward2_next
= Signal()
734 # -- Cache RAM interface
735 # type cache_ram_out_t is array(way_t) of cache_row_t;
736 # signal cache_out : cache_ram_out_t;
737 # Cache RAM interface
739 return Array(Signal(CACHE_ROW
) for x
in range(NUM_WAYS
))
741 cache_out
= CacheRamOut()
743 # -- PLRU output interface
744 # type plru_out_t is array(index_t) of
745 # std_ulogic_vector(WAY_BITS-1 downto 0);
746 # signal plru_victim : plru_out_t;
747 # signal replace_way : way_t;
748 # PLRU output interface
750 return Array(Signal(WAY_BITS
) for x
in range(Index()))
752 plru_victim
= PLRUOut()
753 replace_way
= Signal(WAY
)
755 # -- Wishbone read/write/cache write formatting signals
756 # signal bus_sel : std_ulogic_vector(7 downto 0);
757 # Wishbone read/write/cache write formatting signals
761 # signal tlb_tag_way : tlb_way_tags_t;
762 # signal tlb_pte_way : tlb_way_ptes_t;
763 # signal tlb_valid_way : tlb_way_valids_t;
764 # signal tlb_req_index : tlb_index_t;
765 # signal tlb_hit : std_ulogic;
766 # signal tlb_hit_way : tlb_way_t;
767 # signal pte : tlb_pte_t;
768 # signal ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
769 # signal valid_ra : std_ulogic;
770 # signal perm_attr : perm_attr_t;
771 # signal rc_ok : std_ulogic;
772 # signal perm_ok : std_ulogic;
773 # signal access_ok : std_ulogic;
775 tlb_tag_way
= Signal(TLB_WAY_TAGS
)
776 tlb_pte_way
= Signal(TLB_WAY_PTES
)
777 tlb_valid_way
= Signal(TLB_WAY_VALID_BITS
)
778 tlb_req_index
= Signal(TLB_SET_SIZE
)
780 tlb_hit_way
= Signal(TLB_WAY
)
781 pte
= Signal(TLB_PTE
)
782 ra
= Signal(REAL_ADDR_BITS
)
784 perm_attr
= PermAttr()
789 # -- TLB PLRU output interface
790 # type tlb_plru_out_t is array(tlb_index_t) of
791 # std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
792 # signal tlb_plru_victim : tlb_plru_out_t;
793 # TLB PLRU output interface
795 return Array(Signal(TLB_WAY_BITS
) for x
in range(TLB_SET_SIZE
))
797 tlb_plru_victim
= TLBPLRUOut()
799 # -- Helper functions to decode incoming requests
801 # -- Return the cache line index (tag index) for an address
802 # function get_index(addr: std_ulogic_vector) return index_t is
805 # unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS))
808 # Helper functions to decode incoming requests
810 # Return the cache line index (tag index) for an address
812 return addr
[LINE_OFF_BITS
:SET_SIZE_BITS
]
814 # -- Return the cache row index (data memory) for an address
815 # function get_row(addr: std_ulogic_vector) return row_t is
818 # unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS))
821 # Return the cache row index (data memory) for an address
823 return addr
[ROW_OFF_BITS
:SET_SIZE_BITS
]
825 # -- Return the index of a row within a line
826 # function get_row_of_line(row: row_t) return row_in_line_t is
827 # variable row_v : unsigned(ROW_BITS-1 downto 0);
829 # row_v := to_unsigned(row, ROW_BITS);
830 # return row_v(ROW_LINEBITS-1 downto 0);
832 # Return the index of a row within a line
833 def get_row_of_line(row
):
834 row_v
= Signal(ROW_BITS
)
836 return row_v
[0:ROW_LINE_BITS
]
838 # -- Returns whether this is the last row of a line
839 # function is_last_row_addr(addr: wishbone_addr_type;
840 # last: row_in_line_t) return boolean is
843 # unsigned(addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)) = last;
845 # Returns whether this is the last row of a line
846 def is_last_row_addr(addr
, last
):
847 return addr
[ROW_OFF_BITS
:LINE_OFF_BITS
] == last
849 # -- Returns whether this is the last row of a line
850 # function is_last_row(row: row_t; last: row_in_line_t)
853 # return get_row_of_line(row) = last;
855 # Returns whether this is the last row of a line
856 def is_last_row(row
, last
):
857 return get_row_of_line(row
) == last
859 # -- Return the address of the next row in the current cache line
860 # function next_row_addr(addr: wishbone_addr_type)
861 # return std_ulogic_vector is
862 # variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
863 # variable result : wishbone_addr_type;
865 # -- Is there no simpler way in VHDL to
866 # -- generate that 3 bits adder ?
867 # row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
868 # row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
870 # result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
873 # Return the address of the next row in the current cache line
874 def next_row_addr(addr
):
875 row_idx
= Signal(ROW_LINE_BITS
)
876 result
= WBAddrType()
877 # Is there no simpler way in VHDL to
878 # generate that 3 bits adder ?
879 row_idx
= addr
[ROW_OFF_BITS
:LINE_OFF_BITS
]
880 row_idx
= Signal(row_idx
+ 1)
882 result
[ROW_OFF_BITS
:LINE_OFF_BITS
] = row_idx
885 # -- Return the next row in the current cache line. We use a
886 # -- dedicated function in order to limit the size of the
887 # -- generated adder to be only the bits within a cache line
888 # -- (3 bits with default settings)
889 # function next_row(row: row_t) return row_t is
890 # variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
891 # variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
892 # variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
894 # row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
895 # row_idx := row_v(ROW_LINEBITS-1 downto 0);
896 # row_v(ROW_LINEBITS-1 downto 0) :=
897 # std_ulogic_vector(unsigned(row_idx) + 1);
898 # return to_integer(unsigned(row_v));
900 # Return the next row in the current cache line. We use a
901 # dedicated function in order to limit the size of the
902 # generated adder to be only the bits within a cache line
903 # (3 bits with default settings)
905 row_v
= Signal(ROW_BITS
)
906 row_idx
= Signal(ROW_LINE_BITS
)
907 result
= Signal(ROW_BITS
)
910 row_idx
= row_v
[ROW_LINE_BITS
]
911 row_v
[0:ROW_LINE_BITS
] = Signal(row_idx
+ 1)
914 # -- Get the tag value from the address
915 # function get_tag(addr: std_ulogic_vector) return cache_tag_t is
917 # return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
919 # Get the tag value from the address
921 return addr
[SET_SIZE_BITS
:REAL_ADDR_BITS
]
923 # -- Read a tag from a tag memory row
924 # function read_tag(way: way_t; tagset: cache_tags_set_t)
925 # return cache_tag_t is
927 # return tagset(way * TAG_WIDTH + TAG_BITS
928 # - 1 downto way * TAG_WIDTH);
930 # Read a tag from a tag memory row
931 def read_tag(way
, tagset
):
932 return tagset
[way
*TAG_WIDTH
:way
* TAG_WIDTH
+ TAG_BITS
]
934 # -- Read a TLB tag from a TLB tag memory row
935 # function read_tlb_tag(way: tlb_way_t; tags: tlb_way_tags_t)
936 # return tlb_tag_t is
937 # variable j : integer;
939 # j := way * TLB_EA_TAG_BITS;
940 # return tags(j + TLB_EA_TAG_BITS - 1 downto j);
942 # Read a TLB tag from a TLB tag memory row
943 def read_tlb_tag(way
, tags
):
946 j
= way
* TLB_EA_TAG_BITS
947 return tags
[j
:j
+ TLB_EA_TAG_BITS
]
949 # -- Write a TLB tag to a TLB tag memory row
950 # procedure write_tlb_tag(way: tlb_way_t; tags: inout tlb_way_tags_t;
952 # variable j : integer;
954 # j := way * TLB_EA_TAG_BITS;
955 # tags(j + TLB_EA_TAG_BITS - 1 downto j) := tag;
957 # Write a TLB tag to a TLB tag memory row
958 def write_tlb_tag(way
, tags
), tag
):
961 j
= way
* TLB_EA_TAG_BITS
962 tags
[j
:j
+ TLB_EA_TAG_BITS
] = tag
964 # -- Read a PTE from a TLB PTE memory row
965 # function read_tlb_pte(way: tlb_way_t; ptes: tlb_way_ptes_t)
966 # return tlb_pte_t is
967 # variable j : integer;
969 # j := way * TLB_PTE_BITS;
970 # return ptes(j + TLB_PTE_BITS - 1 downto j);
972 # Read a PTE from a TLB PTE memory row
973 def read_tlb_pte(way
, ptes
):
976 j
= way
* TLB_PTE_BITS
977 return ptes
[j
:j
+ TLB_PTE_BITS
]
979 # procedure write_tlb_pte(way: tlb_way_t;
980 # ptes: inout tlb_way_ptes_t; newpte: tlb_pte_t) is
981 # variable j : integer;
983 # j := way * TLB_PTE_BITS;
984 # ptes(j + TLB_PTE_BITS - 1 downto j) := newpte;
986 def write_tlb_pte(way
, ptes
,newpte
):
989 j
= way
* TLB_PTE_BITS
990 return ptes
[j
:j
+ TLB_PTE_BITS
] = newpte
994 """these, because they are constants, can actually be done *as*
996 assert LINE_SIZE % ROWSIZE == 0, "line size not ...."
998 # assert LINE_SIZE mod ROW_SIZE = 0
999 # report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
1000 # assert ispow2(LINE_SIZE)
1001 # report "LINE_SIZE not power of 2" severity FAILURE;
1002 # assert ispow2(NUM_LINES)
1003 # report "NUM_LINES not power of 2" severity FAILURE;
1004 # assert ispow2(ROW_PER_LINE)
1005 # report "ROW_PER_LINE not power of 2" severity FAILURE;
1006 # assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
1007 # report "geometry bits don't add up" severity FAILURE;
1008 # assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
1009 # report "geometry bits don't add up" severity FAILURE;
1010 # assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
1011 # report "geometry bits don't add up" severity FAILURE;
1012 # assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
1013 # report "geometry bits don't add up" severity FAILURE;
1014 # assert (64 = wishbone_data_bits)
1015 # report "Can't yet handle a wishbone width that isn't 64-bits"
1017 # assert SET_SIZE_BITS <= TLB_LG_PGSZ
1018 # report "Set indexed by virtual address" severity FAILURE;
1019 assert (LINE_SIZE
% ROW_SIZE
) == 0 "LINE_SIZE not " \
1020 "multiple of ROW_SIZE"
1022 assert (LINE_SIZE
% 2) == 0 "LINE_SIZE not power of 2"
1024 assert (NUM_LINES
% 2) == 0 "NUM_LINES not power of 2"
1026 assert (ROW_PER_LINE
% 2) == 0 "ROW_PER_LINE not" \
1029 assert ROW_BITS
== (INDEX_BITS
+ ROW_LINE_BITS
) \
1030 "geometry bits don't add up"
1032 assert (LINE_OFF_BITS
= ROW_OFF_BITS
+ ROW_LINEBITS
) \
1033 "geometry bits don't add up"
1035 assert REAL_ADDR_BITS
== (TAG_BITS
+ INDEX_BITS \
1036 + LINE_OFF_BITS
) "geometry bits don't add up"
1038 assert REAL_ADDR_BITS
== (TAG_BITS
+ ROW_BITS
+ ROW_OFF_BITS
) \
1039 "geometry bits don't add up"
1041 assert 64 == wishbone_data_bits
"Can't yet handle a" \
1042 "wishbone width that isn't 64-bits"
1044 assert SET_SIZE_BITS
<= TLB_LG_PGSZ
"Set indexed by" \
1047 # -- Latch the request in r0.req as long as we're not stalling
1048 # stage_0 : process(clk)
1049 # Latch the request in r0.req as long as we're not stalling
1050 class Stage0(Elaboratable
):
1054 def elaborate(self
, platform
):
1060 # variable r : reg_stage_0_t;
1065 # if rising_edge(clk) then
1066 # assert (d_in.valid and m_in.valid) = '0'
1067 # report "request collision loadstore vs MMU";
1068 assert ~
(d_in
.valid
& m_in
.valid
) "request collision
1071 # if m_in.valid = '1' then
1072 with m
.If(m_in
.valid
):
1073 # r.req.valid := '1';
1074 # r.req.load := not (m_in.tlbie or m_in.tlbld);
1075 # r.req.dcbz := '0';
1077 # r.req.reserve := '0';
1078 # r.req.virt_mode := '0';
1079 # r.req.priv_mode := '1';
1080 # r.req.addr := m_in.addr;
1081 # r.req.data := m_in.pte;
1082 # r.req.byte_sel := (others => '1');
1083 # r.tlbie := m_in.tlbie;
1084 # r.doall := m_in.doall;
1085 # r.tlbld := m_in.tlbld;
1087 sync
+= r
.req
.valid
.eq(1)
1088 sync
+= r
.req
.load
.eq(~
(m_in
.tlbie | m_in
.tlbld
))
1089 sync
+= r
.req
.priv_mode
.eq(1)
1090 sync
+= r
.req
.addr
.eq(m_in
.addr
)
1091 sync
+= r
.req
.data
.eq(m_in
.pte
)
1092 sync
+= r
.req
.byte_sel
.eq(1)
1093 sync
+= r
.tlbie
.eq(m_in
.tlbie
)
1094 sync
+= r
.doall
.eq(m_in
.doall
)
1095 sync
+= r
.tlbld
.eq(m_in
.tlbld
)
1096 sync
+= r
.mmu_req
.eq(1)
1104 sync
+= r
.req
.eq(d_in
)
1108 # elsif r1.full = '0' or r0_full = '0' then
1109 with m
.If(~r1
.full | ~r0_full
):
1111 # r0_full <= r.req.valid;
1113 sync
+= r0_full
.eq(r
.req
.valid
)
1118 # -- we don't yet handle collisions between loadstore1 requests
1119 # -- and MMU requests
1120 # m_out.stall <= '0';
1121 # we don't yet handle collisions between loadstore1 requests
1123 comb
+= m_out
.stall
.eq(0)
1125 # -- Hold off the request in r0 when r1 has an uncompleted request
1126 # r0_stall <= r0_full and r1.full;
1127 # r0_valid <= r0_full and not r1.full;
1128 # stall_out <= r0_stall;
1129 # Hold off the request in r0 when r1 has an uncompleted request
1130 comb
+= r0_stall
.eq(r0_full
& r1
.full
)
1131 comb
+= r0_valid
.eq(r0_full
& ~r1
.full
)
1132 comb
+= stall_out
.eq(r0_stall
)
1135 # -- Operates in the second cycle on the request latched in r0.req.
1136 # -- TLB updates write the entry at the end of the second cycle.
1137 # tlb_read : process(clk)
1139 # Operates in the second cycle on the request latched in r0.req.
1140 # TLB updates write the entry at the end of the second cycle.
1141 class TLBRead(Elaboratable
):
1145 def elaborate(self
, platform
):
1151 # variable index : tlb_index_t;
1152 # variable addrbits :
1153 # std_ulogic_vector(TLB_SET_BITS - 1 downto 0);
1154 index
= TLB_SET_SIZE
1155 addrbits
= Signal(TLB_SET_BITS
)
1161 # if rising_edge(clk) then
1162 # if m_in.valid = '1' then
1163 with m
.If(m_in
.valid
):
1164 # addrbits := m_in.addr(TLB_LG_PGSZ + TLB_SET_BITS
1165 # - 1 downto TLB_LG_PGSZ);
1166 sync
+= addrbits
.eq(m_in
.addr
[
1167 TLB_LG_PGSZ
:TLB_LG_PGSZ
+ TLB_SET_BITS
1171 # addrbits := d_in.addr(TLB_LG_PGSZ + TLB_SET_BITS
1172 # - 1 downto TLB_LG_PGSZ);
1173 sync
+= addrbits
.eq(d_in
.addr
[
1174 TLB_LG_PGSZ
:TLB_LG_PGSZ
+ TLB_SET_BITS
1178 # index := to_integer(unsigned(addrbits));
1179 sync
+= index
.eq(addrbits
)
1180 # -- If we have any op and the previous op isn't finished,
1181 # -- then keep the same output for next cycle.
1182 # if r0_stall = '0' then
1183 # If we have any op and the previous op isn't finished,
1184 # then keep the same output for next cycle.
1185 with m
.If(~r0_stall
):
1186 sync
+= tlb_valid_way
.eq(dtlb_valids
[index
])
1187 sync
+= tlb_tag_way
.eq(dtlb_tags
[index
])
1188 sync
+= tlb_pte_way
.eq(dtlb_ptes
[index
])
1193 # -- Generate TLB PLRUs
1194 # maybe_tlb_plrus: if TLB_NUM_WAYS > 1 generate
1195 # Generate TLB PLRUs
1196 class MaybeTLBPLRUs(Elaboratable
):
1200 def elaborate(self
, platform
):
1206 with m
.If(TLB_NUM_WAYS
> 1):
1208 # TODO understand how to conver generate statements
1209 # tlb_plrus: for i in 0 to TLB_SET_SIZE - 1 generate
1210 # -- TLB PLRU interface
1211 # signal tlb_plru_acc :
1212 # std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
1213 # signal tlb_plru_acc_en : std_ulogic;
1214 # signal tlb_plru_out :
1215 # std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
1217 # tlb_plru : entity work.plru
1219 # BITS => TLB_WAY_BITS
1224 # acc => tlb_plru_acc,
1225 # acc_en => tlb_plru_acc_en,
1226 # lru => tlb_plru_out
1232 # if r1.tlb_hit_index = i then
1233 # tlb_plru_acc_en <= r1.tlb_hit;
1235 # tlb_plru_acc_en <= '0';
1238 # std_ulogic_vector(to_unsigned(
1239 # r1.tlb_hit_way, TLB_WAY_BITS
1241 # tlb_plru_victim(i) <= tlb_plru_out;
1247 # tlb_search : process(all)
1248 class TLBSearch(Elaboratable
):
1252 def elborate(self
, platform
):
1258 # variable hitway : tlb_way_t;
1259 # variable hit : std_ulogic;
1260 # variable eatag : tlb_tag_t;
1271 # to_integer(unsigned(r0.req.addr(
1272 # TLB_LG_PGSZ + TLB_SET_BITS - 1 downto TLB_LG_PGSZ
1276 # eatag := r0.req.addr(63 downto TLB_LG_PGSZ + TLB_SET_BITS);
1277 # for i in tlb_way_t loop
1278 # if tlb_valid_way(i) = '1' and
1279 # read_tlb_tag(i, tlb_tag_way) = eatag then
1284 # tlb_hit <= hit and r0_valid;
1285 # tlb_hit_way <= hitway;
1286 comb
+= tlb_req_index
.eq(r0
.req
.addr
[
1287 TLB_LG_PGSZ
:TLB_LG_PGSZ
+ TLB_SET_BITS
1290 comb
+= eatag
.eq(r0
.req
.addr
[
1291 TLB_LG_PGSZ
+ TLB_SET_BITS
:64
1295 with m
.If(tlb_valid_way(i
)
1296 & read_tlb_tag(i
, tlb_tag_way
) == eatag
):
1298 comb
+= hitway
.eq(i
)
1301 comb
+= tlb_hit
.eq(hit
& r0_valid
)
1302 comb
+= tlb_hit_way
.eq(hitway
)
1304 # if tlb_hit = '1' then
1306 # pte <= read_tlb_pte(hitway, tlb_pte_way);
1307 comb
+= pte
.eq(read_tlb_pte(hitway
, tlb_pte_way
))
1310 # pte <= (others => '0');
1313 # valid_ra <= tlb_hit or not r0.req.virt_mode;
1314 comb
+= valid_ra
.eq(tlb_hit | ~r0
.req
.virt_mode
)
1315 # if r0.req.virt_mode = '1' then
1316 with m
.If(r0
.req
.virt_mode
):
1317 # ra <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
1318 # r0.req.addr(TLB_LG_PGSZ - 1 downto ROW_OFF_BITS) &
1319 # (ROW_OFF_BITS-1 downto 0 => '0');
1320 # perm_attr <= extract_perm_attr(pte);
1322 Const(ROW_OFF_BITS
, ROW_OFF_BITS
),
1323 r0
.req
.addr
[ROW_OFF_BITS
:TLB_LG_PGSZ
],
1324 pte
[TLB_LG_PGSZ
:REAL_ADDR_BITS
]
1326 comb
+= perm_attr
.eq(extract_perm_attr(pte
))
1329 # ra <= r0.req.addr(
1330 # REAL_ADDR_BITS - 1 downto ROW_OFF_BITS
1331 # ) & (ROW_OFF_BITS-1 downto 0 => '0');
1333 Const(ROW_OFF_BITS
, ROW_OFF_BITS
),
1334 r0
.rq
.addr
[ROW_OFF_BITS
:REAL_ADDR_BITS
]
1337 # perm_attr <= real_mode_perm_attr;
1338 comb
+= perm_attr
.eq(real_mode_perm_attr
)
1342 # tlb_update : process(clk)
1343 class TLBUpdate(Elaboratable
):
1347 def elaborate(self
, platform
):
1353 # variable tlbie : std_ulogic;
1354 # variable tlbwe : std_ulogic;
1355 # variable repl_way : tlb_way_t;
1356 # variable eatag : tlb_tag_t;
1357 # variable tagset : tlb_way_tags_t;
1358 # variable pteset : tlb_way_ptes_t;
1363 tagset
= TLBWayTags()
1364 pteset
= TLBWayPtes()
1374 # if rising_edge(clk) then
1375 # tlbie := r0_valid and r0.tlbie;
1376 # tlbwe := r0_valid and r0.tlbldoi;
1377 sync
+= tlbie
.eq(r0_valid
& r0
.tlbie
)
1378 sync
+= tlbwe
.eq(r0_valid
& r0
.tlbldoi
)
1380 # if rst = '1' or (tlbie = '1' and r0.doall = '1') then
1381 # with m.If (TODO understand how signal resets work in nmigen)
1382 # -- clear all valid bits at once
1383 # for i in tlb_index_t loop
1384 # dtlb_valids(i) <= (others => '0');
1386 # clear all valid bits at once
1387 for i
in range(TLB_SET_SIZE
):
1388 sync
+= dtlb_valids
[i
].eq(0)
1389 # elsif tlbie = '1' then
1391 # if tlb_hit = '1' then
1393 # dtlb_valids(tlb_req_index)(tlb_hit_way) <= '0';
1394 sync
+= dtlb_valids
[tlb_req_index
][tlb_hit_way
].eq(0)
1396 # elsif tlbwe = '1' then
1398 # if tlb_hit = '1' then
1400 # repl_way := tlb_hit_way;
1401 sync
+= repl_way
.eq(tlb_hit_way
)
1404 # repl_way := to_integer(unsigned(
1405 # tlb_plru_victim(tlb_req_index)));
1406 sync
+= repl_way
.eq(tlb_plru_victim
[tlb_req_index
])
1408 # eatag := r0.req.addr(
1409 # 63 downto TLB_LG_PGSZ + TLB_SET_BITS
1411 # tagset := tlb_tag_way;
1412 # write_tlb_tag(repl_way, tagset, eatag);
1413 # dtlb_tags(tlb_req_index) <= tagset;
1414 # pteset := tlb_pte_way;
1415 # write_tlb_pte(repl_way, pteset, r0.req.data);
1416 # dtlb_ptes(tlb_req_index) <= pteset;
1417 # dtlb_valids(tlb_req_index)(repl_way) <= '1';
1418 sync
+= eatag
.eq(r0
.req
.addr
[TLB_LG_PGSZ
+ TLB_SET_BITS
:64])
1419 sync
+= tagset
.eq(tlb_tag_way
)
1420 sync
+= write_tlb_tag(repl_way
, tagset
, eatag
)
1421 sync
+= dtlb_tags
[tlb_req_index
].eq(tagset
)
1422 sync
+= pteset
.eq(tlb_pte_way
)
1423 sync
+= write_tlb_pte(repl_way
, pteset
, r0
.req
.data
)
1424 sync
+= dtlb_ptes
[tlb_req_index
].eq(pteset
)
1425 sync
+= dtlb_valids
[tlb_req_index
][repl_way
].eq(1)
1431 # maybe_plrus: if NUM_WAYS > 1 generate
1432 class MaybePLRUs(Elaboratable
):
1436 def elaborate(self
, platform
):
1443 # TODO learn translation of generate into nmgien @lkcl
1444 # plrus: for i in 0 to NUM_LINES-1 generate
1446 # signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
1447 # signal plru_acc_en : std_ulogic;
1448 # signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
1451 # TODO learn tranlation of entity, generic map, port map in
1453 # plru : entity work.plru
1461 # acc_en => plru_acc_en,
1468 # if r1.hit_index = i then
1469 # plru_acc_en <= r1.cache_hit;
1471 # plru_acc_en <= '0';
1473 # plru_acc <= std_ulogic_vector(to_unsigned(
1474 # r1.hit_way, WAY_BITS
1476 # plru_victim(i) <= plru_out;
1481 # -- Cache tag RAM read port
1482 # cache_tag_read : process(clk)
1483 # variable index : index_t;
1485 # if rising_edge(clk) then
1486 # if r0_stall = '1' then
1487 # index := req_index;
1488 # elsif m_in.valid = '1' then
1489 # index := get_index(m_in.addr);
1491 # index := get_index(d_in.addr);
1493 # cache_tag_set <= cache_tags(index);
1497 # -- Cache request parsing and hit detection
1498 # dcache_request : process(all)
1499 # variable is_hit : std_ulogic;
1500 # variable hit_way : way_t;
1501 # variable op : op_t;
1502 # variable opsel : std_ulogic_vector(2 downto 0);
1503 # variable go : std_ulogic;
1504 # variable nc : std_ulogic;
1505 # variable s_hit : std_ulogic;
1506 # variable s_tag : cache_tag_t;
1507 # variable s_pte : tlb_pte_t;
1508 # variable s_ra : std_ulogic_vector(
1509 # REAL_ADDR_BITS - 1 downto 0
1511 # variable hit_set : std_ulogic_vector(
1512 # TLB_NUM_WAYS - 1 downto 0
1514 # variable hit_way_set : hit_way_set_t;
1515 # variable rel_matches : std_ulogic_vector(
1516 # TLB_NUM_WAYS - 1 downto 0
1518 # variable rel_match : std_ulogic;
1520 # -- Extract line, row and tag from request
1521 # req_index <= get_index(r0.req.addr);
1522 # req_row <= get_row(r0.req.addr);
1523 # req_tag <= get_tag(ra);
1525 # go := r0_valid and not (r0.tlbie or r0.tlbld)
1526 # and not r1.ls_error;
1528 # -- Test if pending request is a hit on any way
1529 # -- In order to make timing in virtual mode,
1530 # -- when we are using the TLB, we compare each
1531 # --way with each of the real addresses from each way of
1532 # -- the TLB, and then decide later which match to use.
1536 # if r0.req.virt_mode = '1' then
1537 # rel_matches := (others => '0');
1538 # for j in tlb_way_t loop
1539 # hit_way_set(j) := 0;
1541 # s_pte := read_tlb_pte(j, tlb_pte_way);
1543 # s_pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ)
1544 # & r0.req.addr(TLB_LG_PGSZ - 1 downto 0);
1545 # s_tag := get_tag(s_ra);
1546 # for i in way_t loop
1547 # if go = '1' and cache_valids(req_index)(i) = '1'
1548 # and read_tag(i, cache_tag_set) = s_tag
1549 # and tlb_valid_way(j) = '1' then
1550 # hit_way_set(j) := i;
1554 # hit_set(j) := s_hit;
1555 # if s_tag = r1.reload_tag then
1556 # rel_matches(j) := '1';
1559 # if tlb_hit = '1' then
1560 # is_hit := hit_set(tlb_hit_way);
1561 # hit_way := hit_way_set(tlb_hit_way);
1562 # rel_match := rel_matches(tlb_hit_way);
1565 # s_tag := get_tag(r0.req.addr);
1566 # for i in way_t loop
1567 # if go = '1' and cache_valids(req_index)(i) = '1' and
1568 # read_tag(i, cache_tag_set) = s_tag then
1573 # if s_tag = r1.reload_tag then
1577 # req_same_tag <= rel_match;
1579 # -- See if the request matches the line currently being reloaded
1580 # if r1.state = RELOAD_WAIT_ACK and req_index = r1.store_index
1581 # and rel_match = '1' then
1582 # -- For a store, consider this a hit even if the row isn't
1583 # -- valid since it will be by the time we perform the store.
1584 # -- For a load, check the appropriate row valid bit.
1586 # not r0.req.load or r1.rows_valid(req_row mod ROW_PER_LINE);
1587 # hit_way := replace_way;
1590 # -- Whether to use forwarded data for a load or not
1591 # use_forward1_next <= '0';
1592 # if get_row(r1.req.real_addr) = req_row
1593 # and r1.req.hit_way = hit_way then
1594 # -- Only need to consider r1.write_bram here, since if we
1595 # -- are writing refill data here, then we don't have a
1596 # -- cache hit this cycle on the line being refilled.
1597 # -- (There is the possibility that the load following the
1598 # -- load miss that started the refill could be to the old
1599 # -- contents of the victim line, since it is a couple of
1600 # -- cycles after the refill starts before we see the updated
1601 # -- cache tag. In that case we don't use the bypass.)
1602 # use_forward1_next <= r1.write_bram;
1604 # use_forward2_next <= '0';
1605 # if r1.forward_row1 = req_row and r1.forward_way1 = hit_way then
1606 # use_forward2_next <= r1.forward_valid1;
1609 # -- The way that matched on a hit
1610 # req_hit_way <= hit_way;
1612 # -- The way to replace on a miss
1613 # if r1.write_tag = '1' then
1614 # replace_way <= to_integer(unsigned(
1615 # plru_victim(r1.store_index)
1618 # replace_way <= r1.store_way;
1621 # -- work out whether we have permission for this access
1622 # -- NB we don't yet implement AMR, thus no KUAP
1623 # rc_ok <= perm_attr.reference and
1624 # (r0.req.load or perm_attr.changed);
1625 # perm_ok <= (r0.req.priv_mode or not perm_attr.priv) and
1626 # (perm_attr.wr_perm or (r0.req.load
1627 # and perm_attr.rd_perm));
1628 # access_ok <= valid_ra and perm_ok and rc_ok;
1630 # -- Combine the request and cache hit status to decide what
1631 # -- operation needs to be done
1633 # nc := r0.req.nc or perm_attr.nocache;
1636 # if access_ok = '0' then
1638 # elsif cancel_store = '1' then
1639 # op := OP_STCX_FAIL;
1641 # opsel := r0.req.load & nc & is_hit;
1643 # when "101" => op := OP_LOAD_HIT;
1644 # when "100" => op := OP_LOAD_MISS;
1645 # when "110" => op := OP_LOAD_NC;
1646 # when "001" => op := OP_STORE_HIT;
1647 # when "000" => op := OP_STORE_MISS;
1648 # when "010" => op := OP_STORE_MISS;
1649 # when "011" => op := OP_BAD;
1650 # when "111" => op := OP_BAD;
1651 # when others => op := OP_NONE;
1658 # -- Version of the row number that is valid one cycle earlier
1659 # -- in the cases where we need to read the cache data BRAM.
1660 # -- If we're stalling then we need to keep reading the last
1662 # if r0_stall = '0' then
1663 # if m_in.valid = '1' then
1664 # early_req_row <= get_row(m_in.addr);
1666 # early_req_row <= get_row(d_in.addr);
1669 # early_req_row <= req_row;
1673 # -- Wire up wishbone request latch out of stage 1
1674 # wishbone_out <= r1.wb;
1676 # -- Handle load-with-reservation and store-conditional instructions
1677 # reservation_comb: process(all)
1679 # cancel_store <= '0';
1681 # clear_rsrv <= '0';
1682 # if r0_valid = '1' and r0.req.reserve = '1' then
1683 # -- XXX generate alignment interrupt if address
1684 # -- is not aligned XXX or if r0.req.nc = '1'
1685 # if r0.req.load = '1' then
1686 # -- load with reservation
1689 # -- store conditional
1690 # clear_rsrv <= '1';
1691 # if reservation.valid = '0' or r0.req.addr(63
1692 # downto LINE_OFF_BITS) /= reservation.addr then
1693 # cancel_store <= '1';
1699 # reservation_reg: process(clk)
1701 # if rising_edge(clk) then
1703 # reservation.valid <= '0';
1704 # elsif r0_valid = '1' and access_ok = '1' then
1705 # if clear_rsrv = '1' then
1706 # reservation.valid <= '0';
1707 # elsif set_rsrv = '1' then
1708 # reservation.valid <= '1';
1709 # reservation.addr <=
1710 # r0.req.addr(63 downto LINE_OFF_BITS);
1716 # -- Return data for loads & completion control logic
1718 # writeback_control: process(all)
1719 # variable data_out : std_ulogic_vector(63 downto 0);
1720 # variable data_fwd : std_ulogic_vector(63 downto 0);
1721 # variable j : integer;
1723 # -- Use the bypass if are reading the row that was
1724 # -- written 1 or 2 cycles ago, including for the
1725 # -- slow_valid = 1 case (i.e. completing a load
1726 # -- miss or a non-cacheable load).
1727 # if r1.use_forward1 = '1' then
1728 # data_fwd := r1.forward_data1;
1730 # data_fwd := r1.forward_data2;
1732 # data_out := cache_out(r1.hit_way);
1733 # for i in 0 to 7 loop
1735 # if r1.forward_sel(i) = '1' then
1736 # data_out(j + 7 downto j) := data_fwd(j + 7 downto j);
1740 # d_out.valid <= r1.ls_valid;
1741 # d_out.data <= data_out;
1742 # d_out.store_done <= not r1.stcx_fail;
1743 # d_out.error <= r1.ls_error;
1744 # d_out.cache_paradox <= r1.cache_paradox;
1747 # m_out.done <= r1.mmu_done;
1748 # m_out.err <= r1.mmu_error;
1749 # m_out.data <= data_out;
1751 # -- We have a valid load or store hit or we just completed
1752 # -- a slow op such as a load miss, a NC load or a store
1754 # -- Note: the load hit is delayed by one cycle. However it
1755 # -- can still not collide with r.slow_valid (well unless I
1756 # -- miscalculated) because slow_valid can only be set on a
1757 # -- subsequent request and not on its first cycle (the state
1758 # -- machine must have advanced), which makes slow_valid
1759 # -- at least 2 cycles from the previous hit_load_valid.
1761 # -- Sanity: Only one of these must be set in any given cycle
1762 # assert (r1.slow_valid and r1.stcx_fail) /= '1'
1763 # report "unexpected slow_valid collision with stcx_fail"
1765 # assert ((r1.slow_valid or r1.stcx_fail) and r1.hit_load_valid)
1766 # /= '1' report "unexpected hit_load_delayed collision with
1767 # slow_valid" severity FAILURE;
1769 # if r1.mmu_req = '0' then
1770 # -- Request came from loadstore1...
1771 # -- Load hit case is the standard path
1772 # if r1.hit_load_valid = '1' then
1774 # "completing load hit data=" & to_hstring(data_out);
1777 # -- error cases complete without stalling
1778 # if r1.ls_error = '1' then
1779 # report "completing ld/st with error";
1782 # -- Slow ops (load miss, NC, stores)
1783 # if r1.slow_valid = '1' then
1785 # "completing store or load miss data="
1786 # & to_hstring(data_out);
1790 # -- Request came from MMU
1791 # if r1.hit_load_valid = '1' then
1792 # report "completing load hit to MMU, data="
1793 # & to_hstring(m_out.data);
1796 # -- error cases complete without stalling
1797 # if r1.mmu_error = '1' then
1798 # report "completing MMU ld with error";
1801 # -- Slow ops (i.e. load miss)
1802 # if r1.slow_valid = '1' then
1803 # report "completing MMU load miss, data="
1804 # & to_hstring(m_out.data);
1811 # -- Generate a cache RAM for each way. This handles the normal
1812 # -- reads, writes from reloads and the special store-hit update
1815 # -- Note: the BRAMs have an extra read buffer, meaning the output
1816 # -- is pipelined an extra cycle. This differs from the
1817 # -- icache. The writeback logic needs to take that into
1818 # -- account by using 1-cycle delayed signals for load hits.
1820 # rams: for i in 0 to NUM_WAYS-1 generate
1821 # signal do_read : std_ulogic;
1822 # signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
1823 # signal do_write : std_ulogic;
1824 # signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
1826 # std_ulogic_vector(wishbone_data_bits-1 downto 0);
1827 # signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
1828 # signal wr_sel_m : std_ulogic_vector(ROW_SIZE-1 downto 0);
1829 # signal dout : cache_row_t;
1831 # way: entity work.cache_ram
1833 # ROW_BITS => ROW_BITS,
1834 # WIDTH => wishbone_data_bits,
1840 # rd_addr => rd_addr,
1842 # wr_sel => wr_sel_m,
1843 # wr_addr => wr_addr,
1844 # wr_data => wr_data
1848 # -- Cache hit reads
1851 # std_ulogic_vector(to_unsigned(early_req_row, ROW_BITS));
1852 # cache_out(i) <= dout;
1856 # -- Defaults to wishbone read responses (cache refill)
1858 # -- For timing, the mux on wr_data/sel/addr is not
1859 # -- dependent on anything other than the current state.
1860 # wr_sel_m <= (others => '0');
1863 # if r1.write_bram = '1' then
1864 # -- Write store data to BRAM. This happens one
1865 # -- cycle after the store is in r0.
1866 # wr_data <= r1.req.data;
1867 # wr_sel <= r1.req.byte_sel;
1868 # wr_addr <= std_ulogic_vector(to_unsigned(
1869 # get_row(r1.req.real_addr), ROW_BITS
1871 # if i = r1.req.hit_way then
1875 # -- Otherwise, we might be doing a reload or a DCBZ
1876 # if r1.dcbz = '1' then
1877 # wr_data <= (others => '0');
1879 # wr_data <= wishbone_in.dat;
1881 # wr_addr <= std_ulogic_vector(to_unsigned(
1882 # r1.store_row, ROW_BITS
1884 # wr_sel <= (others => '1');
1886 # if r1.state = RELOAD_WAIT_ACK and
1887 # wishbone_in.ack = '1' and replace_way = i then
1892 # -- Mask write selects with do_write since BRAM
1893 # -- doesn't have a global write-enable
1894 # if do_write = '1' then
1895 # wr_sel_m <= wr_sel;
1901 # -- Cache hit synchronous machine for the easy case.
1902 # -- This handles load hits.
1903 # -- It also handles error cases (TLB miss, cache paradox)
1904 # dcache_fast_hit : process(clk)
1906 # if rising_edge(clk) then
1907 # if req_op /= OP_NONE then
1908 # report "op:" & op_t'image(req_op) &
1909 # " addr:" & to_hstring(r0.req.addr) &
1910 # " nc:" & std_ulogic'image(r0.req.nc) &
1911 # " idx:" & integer'image(req_index) &
1912 # " tag:" & to_hstring(req_tag) &
1913 # " way: " & integer'image(req_hit_way);
1915 # if r0_valid = '1' then
1916 # r1.mmu_req <= r0.mmu_req;
1919 # -- Fast path for load/store hits.
1920 # -- Set signals for the writeback controls.
1921 # r1.hit_way <= req_hit_way;
1922 # r1.hit_index <= req_index;
1923 # if req_op = OP_LOAD_HIT then
1924 # r1.hit_load_valid <= '1';
1926 # r1.hit_load_valid <= '0';
1928 # if req_op = OP_LOAD_HIT or req_op = OP_STORE_HIT then
1929 # r1.cache_hit <= '1';
1931 # r1.cache_hit <= '0';
1934 # if req_op = OP_BAD then
1935 # report "Signalling ld/st error valid_ra=" &
1936 # std_ulogic'image(valid_ra) & " rc_ok=" &
1937 # std_ulogic'image(rc_ok) & " perm_ok=" &
1938 # std_ulogic'image(perm_ok);
1939 # r1.ls_error <= not r0.mmu_req;
1940 # r1.mmu_error <= r0.mmu_req;
1941 # r1.cache_paradox <= access_ok;
1943 # r1.ls_error <= '0';
1944 # r1.mmu_error <= '0';
1945 # r1.cache_paradox <= '0';
1948 # if req_op = OP_STCX_FAIL then
1949 # r1.stcx_fail <= '1';
1951 # r1.stcx_fail <= '0';
1954 # -- Record TLB hit information for updating TLB PLRU
1955 # r1.tlb_hit <= tlb_hit;
1956 # r1.tlb_hit_way <= tlb_hit_way;
1957 # r1.tlb_hit_index <= tlb_req_index;
1962 # -- Memory accesses are handled by this state machine:
1964 # -- * Cache load miss/reload (in conjunction with "rams")
1965 # -- * Load hits for non-cachable forms
1966 # -- * Stores (the collision case is handled in "rams")
1968 # -- All wishbone requests generation is done here.
1969 # -- This machine operates at stage 1.
1970 # dcache_slow : process(clk)
1971 # variable stbs_done : boolean;
1972 # variable req : mem_access_request_t;
1973 # variable acks : unsigned(2 downto 0);
1975 # if rising_edge(clk) then
1976 # r1.use_forward1 <= use_forward1_next;
1977 # r1.forward_sel <= (others => '0');
1978 # if use_forward1_next = '1' then
1979 # r1.forward_sel <= r1.req.byte_sel;
1980 # elsif use_forward2_next = '1' then
1981 # r1.forward_sel <= r1.forward_sel1;
1984 # r1.forward_data2 <= r1.forward_data1;
1985 # if r1.write_bram = '1' then
1986 # r1.forward_data1 <= r1.req.data;
1987 # r1.forward_sel1 <= r1.req.byte_sel;
1988 # r1.forward_way1 <= r1.req.hit_way;
1989 # r1.forward_row1 <= get_row(r1.req.real_addr);
1990 # r1.forward_valid1 <= '1';
1992 # if r1.dcbz = '1' then
1993 # r1.forward_data1 <= (others => '0');
1995 # r1.forward_data1 <= wishbone_in.dat;
1997 # r1.forward_sel1 <= (others => '1');
1998 # r1.forward_way1 <= replace_way;
1999 # r1.forward_row1 <= r1.store_row;
2000 # r1.forward_valid1 <= '0';
2003 # -- On reset, clear all valid bits to force misses
2005 # for i in index_t loop
2006 # cache_valids(i) <= (others => '0');
2010 # r1.slow_valid <= '0';
2013 # r1.ls_valid <= '0';
2014 # r1.mmu_done <= '0';
2016 # -- Not useful normally but helps avoiding
2017 # -- tons of sim warnings
2018 # r1.wb.adr <= (others => '0');
2020 # -- One cycle pulses reset
2021 # r1.slow_valid <= '0';
2022 # r1.write_bram <= '0';
2023 # r1.inc_acks <= '0';
2024 # r1.dec_acks <= '0';
2026 # r1.ls_valid <= '0';
2027 # -- complete tlbies and TLB loads in the third cycle
2028 # r1.mmu_done <= r0_valid and (r0.tlbie or r0.tlbld);
2029 # if req_op = OP_LOAD_HIT or req_op = OP_STCX_FAIL then
2030 # if r0.mmu_req = '0' then
2031 # r1.ls_valid <= '1';
2033 # r1.mmu_done <= '1';
2037 # if r1.write_tag = '1' then
2038 # -- Store new tag in selected way
2039 # for i in 0 to NUM_WAYS-1 loop
2040 # if i = replace_way then
2041 # cache_tags(r1.store_index)(
2042 # (i + 1) * TAG_WIDTH - 1
2043 # downto i * TAG_WIDTH
2045 # (TAG_WIDTH - 1 downto TAG_BITS => '0')
2049 # r1.store_way <= replace_way;
2050 # r1.write_tag <= '0';
2053 # -- Take request from r1.req if there is one there,
2054 # -- else from req_op, ra, etc.
2055 # if r1.full = '1' then
2059 # req.valid := req_go;
2060 # req.mmu_req := r0.mmu_req;
2061 # req.dcbz := r0.req.dcbz;
2062 # req.real_addr := ra;
2063 # -- Force data to 0 for dcbz
2064 # if r0.req.dcbz = '0' then
2065 # req.data := r0.req.data;
2067 # req.data := (others => '0');
2069 # -- Select all bytes for dcbz
2070 # -- and for cacheable loads
2071 # if r0.req.dcbz = '1'
2072 # or (r0.req.load = '1' and r0.req.nc = '0') then
2073 # req.byte_sel := (others => '1');
2075 # req.byte_sel := r0.req.byte_sel;
2077 # req.hit_way := req_hit_way;
2078 # req.same_tag := req_same_tag;
2080 # -- Store the incoming request from r0,
2081 # -- if it is a slow request
2082 # -- Note that r1.full = 1 implies req_op = OP_NONE
2083 # if req_op = OP_LOAD_MISS or req_op = OP_LOAD_NC
2084 # or req_op = OP_STORE_MISS
2085 # or req_op = OP_STORE_HIT then
2091 # -- Main state machine
2094 # r1.wb.adr <= req.real_addr(r1.wb.adr'left downto 0);
2095 # r1.wb.sel <= req.byte_sel;
2096 # r1.wb.dat <= req.data;
2097 # r1.dcbz <= req.dcbz;
2099 # -- Keep track of our index and way
2100 # -- for subsequent stores.
2101 # r1.store_index <= get_index(req.real_addr);
2102 # r1.store_row <= get_row(req.real_addr);
2104 # get_row_of_line(get_row(req.real_addr)) - 1;
2105 # r1.reload_tag <= get_tag(req.real_addr);
2106 # r1.req.same_tag <= '1';
2108 # if req.op = OP_STORE_HIT then
2109 # r1.store_way <= req.hit_way;
2112 # -- Reset per-row valid bits,
2113 # -- ready for handling OP_LOAD_MISS
2114 # for i in 0 to ROW_PER_LINE - 1 loop
2115 # r1.rows_valid(i) <= '0';
2119 # when OP_LOAD_HIT =>
2120 # -- stay in IDLE state
2122 # when OP_LOAD_MISS =>
2123 # -- Normal load cache miss,
2124 # -- start the reload machine
2125 # report "cache miss real addr:" &
2126 # to_hstring(req.real_addr) & " idx:" &
2127 # integer'image(get_index(req.real_addr)) &
2128 # " tag:" & to_hstring(get_tag(req.real_addr));
2130 # -- Start the wishbone cycle
2135 # -- Track that we had one request sent
2136 # r1.state <= RELOAD_WAIT_ACK;
2137 # r1.write_tag <= '1';
2139 # when OP_LOAD_NC =>
2143 # r1.state <= NC_LOAD_WAIT_ACK;
2145 # when OP_STORE_HIT | OP_STORE_MISS =>
2146 # if req.dcbz = '0' then
2147 # r1.state <= STORE_WAIT_ACK;
2148 # r1.acks_pending <= to_unsigned(1, 3);
2150 # r1.slow_valid <= '1';
2151 # if req.mmu_req = '0' then
2152 # r1.ls_valid <= '1';
2154 # r1.mmu_done <= '1';
2156 # if req.op = OP_STORE_HIT then
2157 # r1.write_bram <= '1';
2160 # -- dcbz is handled much like a load
2161 # -- miss except that we are writing
2162 # -- to memory instead of reading
2163 # r1.state <= RELOAD_WAIT_ACK;
2164 # if req.op = OP_STORE_MISS then
2165 # r1.write_tag <= '1';
2172 # -- OP_NONE and OP_BAD do nothing
2173 # -- OP_BAD & OP_STCX_FAIL were handled above already
2176 # when OP_STCX_FAIL =>
2179 # when RELOAD_WAIT_ACK =>
2180 # -- Requests are all sent if stb is 0
2181 # stbs_done := r1.wb.stb = '0';
2183 # -- If we are still sending requests,
2184 # -- was one accepted?
2185 # if wishbone_in.stall = '0' and not stbs_done then
2186 # -- That was the last word ? We are done sending.
2187 # -- Clear stb and set stbs_done so we can handle
2188 # -- an eventual last ack on the same cycle.
2189 # if is_last_row_addr(r1.wb.adr, r1.end_row_ix) then
2191 # stbs_done := true;
2194 # -- Calculate the next row address
2195 # r1.wb.adr <= next_row_addr(r1.wb.adr);
2198 # -- Incoming acks processing
2199 # r1.forward_valid1 <= wishbone_in.ack;
2200 # if wishbone_in.ack = '1' then
2202 # r1.store_row mod ROW_PER_LINE
2204 # -- If this is the data we were looking for,
2205 # -- we can complete the request next cycle.
2206 # -- Compare the whole address in case the
2207 # -- request in r1.req is not the one that
2208 # -- started this refill.
2209 # if r1.full = '1' and r1.req.same_tag = '1'
2210 # and ((r1.dcbz = '1' and r1.req.dcbz = '1')
2211 # or (r1.dcbz = '0' and r1.req.op = OP_LOAD_MISS))
2212 # and r1.store_row = get_row(r1.req.real_addr) then
2214 # r1.slow_valid <= '1';
2215 # if r1.mmu_req = '0' then
2216 # r1.ls_valid <= '1';
2218 # r1.mmu_done <= '1';
2220 # r1.forward_sel <= (others => '1');
2221 # r1.use_forward1 <= '1';
2224 # -- Check for completion
2225 # if stbs_done and is_last_row(r1.store_row,
2226 # r1.end_row_ix) then
2227 # -- Complete wishbone cycle
2230 # -- Cache line is now valid
2231 # cache_valids(r1.store_index)(
2238 # -- Increment store row counter
2239 # r1.store_row <= next_row(r1.store_row);
2242 # when STORE_WAIT_ACK =>
2243 # stbs_done := r1.wb.stb = '0';
2244 # acks := r1.acks_pending;
2245 # if r1.inc_acks /= r1.dec_acks then
2246 # if r1.inc_acks = '1' then
2252 # r1.acks_pending <= acks;
2253 # -- Clear stb when slave accepted request
2254 # if wishbone_in.stall = '0' then
2255 # -- See if there is another store waiting
2256 # -- to be done which is in the same real page.
2257 # if req.valid = '1' then
2259 # SET_SIZE_BITS - 1 downto 0
2260 # ) <= req.real_addr(
2261 # SET_SIZE_BITS - 1 downto 0
2263 # r1.wb.dat <= req.data;
2264 # r1.wb.sel <= req.byte_sel;
2266 # if acks < 7 and req.same_tag = '1'
2267 # and (req.op = OP_STORE_MISS
2268 # or req.op = OP_STORE_HIT) then
2270 # stbs_done := false;
2271 # if req.op = OP_STORE_HIT then
2272 # r1.write_bram <= '1';
2275 # r1.slow_valid <= '1';
2276 # -- Store requests never come from the MMU
2277 # r1.ls_valid <= '1';
2278 # stbs_done := false;
2279 # r1.inc_acks <= '1';
2282 # stbs_done := true;
2286 # -- Got ack ? See if complete.
2287 # if wishbone_in.ack = '1' then
2288 # if stbs_done and acks = 1 then
2293 # r1.dec_acks <= '1';
2296 # when NC_LOAD_WAIT_ACK =>
2297 # -- Clear stb when slave accepted request
2298 # if wishbone_in.stall = '0' then
2302 # -- Got ack ? complete.
2303 # if wishbone_in.ack = '1' then
2306 # r1.slow_valid <= '1';
2307 # if r1.mmu_req = '0' then
2308 # r1.ls_valid <= '1';
2310 # r1.mmu_done <= '1';
2312 # r1.forward_sel <= (others => '1');
2313 # r1.use_forward1 <= '1';
2322 # dc_log: if LOG_LENGTH > 0 generate
2323 # signal log_data : std_ulogic_vector(19 downto 0);
2325 # dcache_log: process(clk)
2327 # if rising_edge(clk) then
2328 # log_data <= r1.wb.adr(5 downto 3) &
2329 # wishbone_in.stall &
2331 # r1.wb.stb & r1.wb.cyc &
2334 # std_ulogic_vector(
2335 # to_unsigned(op_t'pos(req_op), 3)) &
2337 # std_ulogic_vector(
2338 # to_unsigned(tlb_hit_way, 3)) &
2340 # std_ulogic_vector(
2341 # to_unsigned(state_t'pos(r1.state), 3));
2344 # log_out <= log_data;