3 This first version is intended for prototyping and test purposes:
4 it has "direct" access to Memory.
6 The intention is that this version remains an integral part of the
7 test infrastructure, and, just as with minerva's memory arrangement,
8 a dynamic runtime config *selects* alternative memory arrangements
9 rather than *replaces and discards* this code.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
18 from nmigen
.compat
.sim
import run_simulation
19 from nmigen
.cli
import verilog
, rtlil
20 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Array
, Cat
21 from nmutil
.iocontrol
import RecordObject
22 from nmigen
.utils
import log2_int
23 from nmigen
.hdl
.rec
import Record
, Layout
25 from nmutil
.latch
import SRLatch
, latchregister
26 from soc
.decoder
.power_decoder2
import Data
27 from soc
.decoder
.power_enums
import InternalOp
29 from soc
.experiment
.compldst
import CompLDSTOpSubset
30 from soc
.decoder
.power_decoder2
import Data
31 #from nmutil.picker import PriorityPicker
32 from nmigen
.lib
.coding
import PriorityEncoder
34 # for testing purposes
35 from soc
.experiment
.testmem
import TestMemory
38 class PortInterface(RecordObject
):
41 defines the interface - the API - that the LDSTCompUnit connects
42 to. note that this is NOT a "fire-and-forget" interface. the
43 LDSTCompUnit *must* be kept appraised that the request is in
44 progress, and only when it has a 100% successful completion rate
45 can the notification be given (busy dropped).
47 The interface FSM rules are as follows:
49 * if busy_o is asserted, a LD/ST is in progress. further
50 requests may not be made until busy_o is deasserted.
52 * only one of is_ld_i or is_st_i may be asserted. busy_o
53 will immediately be asserted and remain asserted.
55 * addr.ok is to be asserted when the LD/ST address is known.
56 addr.data is to be valid on the same cycle.
58 addr.ok and addr.data must REMAIN asserted until busy_o
59 is de-asserted. this ensures that there is no need
60 for the L0 Cache/Buffer to have an additional address latch
61 (because the LDSTCompUnit already has it)
63 * addr_ok_o (or addr_exc_o) must be waited for. these will
64 be asserted *only* for one cycle and one cycle only.
66 * addr_exc_o will be asserted if there is no chance that the
67 memory request may be fulfilled.
69 busy_o is deasserted on the same cycle as addr_exc_o is asserted.
71 * conversely: addr_ok_o must *ONLY* be asserted if there is a
72 HUNDRED PERCENT guarantee that the memory request will be
75 * for a LD, ld.ok will be asserted - for only one clock cycle -
76 at any point in the future that is acceptable to the underlying
77 Memory subsystem. the recipient MUST latch ld.data on that cycle.
79 busy_o is deasserted on the same cycle as ld.ok is asserted.
81 * for a ST, st.ok may be asserted only after addr_ok_o had been
82 asserted, alongside valid st.data at the same time. st.ok
83 must only be asserted for one cycle.
85 the underlying Memory is REQUIRED to pick up that data and
86 guarantee its delivery. no back-acknowledgement is required.
88 busy_o is deasserted on the cycle AFTER st.ok is asserted.
91 def __init__(self
, name
=None, regwid
=64, addrwid
=48):
94 self
._addrwid
= addrwid
96 RecordObject
.__init
__(self
, name
=name
)
98 # distinguish op type (ld/st)
99 self
.is_ld_i
= Signal(reset_less
=True)
100 self
.is_st_i
= Signal(reset_less
=True)
101 self
.op
= CompLDSTOpSubset() # hm insn_type ld/st duplicates here
104 self
.busy_o
= Signal(reset_less
=True) # do not use if busy
105 self
.go_die_i
= Signal(reset_less
=True) # back to reset
106 self
.addr
= Data(addrwid
, "addr_i") # addr/addr-ok
107 # addr is valid (TLB, L1 etc.)
108 self
.addr_ok_o
= Signal(reset_less
=True)
109 self
.addr_exc_o
= Signal(reset_less
=True) # TODO, "type" of exception
112 self
.ld
= Data(regwid
, "ld_data_o") # ok to be set by L0 Cache/Buf
113 self
.st
= Data(regwid
, "st_data_i") # ok to be set by CompUnit
118 class DualPortSplitter(Elaboratable
):
121 * one incoming PortInterface
122 * two *OUTGOING* PortInterfaces
123 * uses LDSTSplitter to do it
125 (actually, thinking about it LDSTSplitter could simply be
126 modified to conform to PortInterface: one in, two out)
128 once that is done each pair of ports may be wired directly
129 to the dual ports of L0CacheBuffer
134 class DataMergerRecord(Record
):
136 {data: 128 bit, byte_enable: 16 bit}
139 def __init__(self
, name
=None):
140 layout
= (('data', 128),
144 Record
.__init
__(self
, Layout(layout
), name
=name
)
149 class DataMerger(Elaboratable
):
152 Merges data based on an address-match matrix
156 def __init__(self
, array_size
):
158 :addr_array_i: an NxN Array of Signals with bits set indicating address match
159 :data_i: an Nx Array of Records {data: 128 bit, byte_enable: 16 bit}
160 :data_o: an Output Record of same type {data: 128 bit, byte_enable: 16 bit}
162 self
.array_size
= array_size
164 for i
in range(0, array_size
):
166 for j
in range(0, array_size
):
169 self
.addr_array_i
= Array(ul
)
172 for i
in range(0, array_size
):
173 ul
.append(DataMergerRecord())
174 self
.data_i
= Array(ul
)
175 self
.data_o
= DataMergerRecord()
178 class LDSTPort(Elaboratable
):
179 def __init__(self
, idx
, regwid
=64, addrwid
=48):
180 self
.pi
= PortInterface("ldst_port%d" % idx
, regwid
, addrwid
)
182 def elaborate(self
, platform
):
184 comb
, sync
= m
.d
.comb
, m
.d
.sync
187 m
.submodules
.busy_l
= busy_l
= SRLatch(False, name
="busy")
188 m
.submodules
.cyc_l
= cyc_l
= SRLatch(True, name
="cyc")
189 comb
+= cyc_l
.s
.eq(0)
190 comb
+= cyc_l
.r
.eq(0)
192 # this is a little weird: we let the L0Cache/Buffer set
193 # the outputs: this module just monitors "state".
195 # LD/ST requested activates "busy"
196 with m
.If(self
.pi
.is_ld_i | self
.pi
.is_st_i
):
197 comb
+= busy_l
.s
.eq(1)
199 # monitor for an exception or the completion of LD.
200 with m
.If(self
.pi
.addr_exc_o
):
201 comb
+= busy_l
.r
.eq(1)
203 # however ST needs one cycle before busy is reset
204 with m
.If(self
.pi
.st
.ok | self
.pi
.ld
.ok
):
205 comb
+= cyc_l
.s
.eq(1)
208 comb
+= cyc_l
.r
.eq(1)
209 comb
+= busy_l
.r
.eq(1)
211 # busy latch outputs to interface
212 comb
+= self
.pi
.busy_o
.eq(busy_l
.q
)
217 yield self
.pi
.is_ld_i
218 yield self
.pi
.is_st_i
219 yield from self
.pi
.op
.ports()
221 yield self
.pi
.go_die_i
222 yield from self
.pi
.addr
.ports()
223 yield self
.pi
.addr_ok_o
224 yield self
.pi
.addr_exc_o
226 yield from self
.pi
.ld
.ports()
227 yield from self
.pi
.st
.ports()
233 class L0CacheBuffer(Elaboratable
):
236 Note that the final version will have *two* interfaces per LDSTCompUnit,
237 to cover mis-aligned requests, as well as *two* 128-bit L1 Cache
238 interfaces: one for odd (addr[4] == 1) and one for even (addr[4] == 1).
240 This version is to be used for test purposes (and actively maintained
241 for such, rather than "replaced")
243 There are much better ways to implement this. However it's only
244 a "demo" / "test" class, and one important aspect: it responds
245 combinatorially, where a nmigen FSM's state-changes only activate
246 on clock-sync boundaries.
249 def __init__(self
, n_units
, mem
, regwid
=64, addrwid
=48):
250 self
.n_units
= n_units
253 for i
in range(n_units
):
254 ul
.append(LDSTPort(i
, regwid
, addrwid
))
255 self
.dports
= Array(ul
)
257 def elaborate(self
, platform
):
259 comb
, sync
= m
.d
.comb
, m
.d
.sync
261 # connect the ports as modules
262 for i
in range(self
.n_units
):
263 setattr(m
.submodules
, "port%d" % i
, self
.dports
[i
])
265 # state-machine latches
266 m
.submodules
.st_active
= st_active
= SRLatch(False, name
="st_active")
267 m
.submodules
.ld_active
= ld_active
= SRLatch(False, name
="ld_active")
268 m
.submodules
.reset_l
= reset_l
= SRLatch(True, name
="reset")
269 m
.submodules
.idx_l
= idx_l
= SRLatch(False, name
="idx_l")
270 m
.submodules
.adrok_l
= adrok_l
= SRLatch(False, name
="addr_acked")
272 # find one LD (or ST) and do it. only one per cycle.
273 # TODO: in the "live" (production) L0Cache/Buffer, merge multiple
274 # LD/STs using mask-expansion - see LenExpand class
276 m
.submodules
.ldpick
= ldpick
= PriorityEncoder(self
.n_units
)
277 m
.submodules
.stpick
= stpick
= PriorityEncoder(self
.n_units
)
279 lds
= Signal(self
.n_units
, reset_less
=True)
280 sts
= Signal(self
.n_units
, reset_less
=True)
283 for i
in range(self
.n_units
):
284 pi
= self
.dports
[i
].pi
285 ldi
.append(pi
.is_ld_i
& pi
.busy_o
) # accumulate ld-req signals
286 sti
.append(pi
.is_st_i
& pi
.busy_o
) # accumulate st-req signals
287 # put the requests into the priority-pickers
288 comb
+= ldpick
.i
.eq(Cat(*ldi
))
289 comb
+= stpick
.i
.eq(Cat(*sti
))
291 # hmm, have to select (record) the right port index
292 nbits
= log2_int(self
.n_units
, False)
293 ld_idx
= Signal(nbits
, reset_less
=False)
294 st_idx
= Signal(nbits
, reset_less
=False)
295 # use these because of the sync-and-comb pass-through capability
296 latchregister(m
, ldpick
.o
, ld_idx
, idx_l
.qn
, name
="ld_idx_l")
297 latchregister(m
, stpick
.o
, st_idx
, idx_l
.qn
, name
="st_idx_l")
299 # convenience variables to reference the "picked" port
300 ldport
= self
.dports
[ld_idx
].pi
301 stport
= self
.dports
[st_idx
].pi
302 # and the memory ports
303 rdport
= self
.mem
.rdport
304 wrport
= self
.mem
.wrport
306 # Priority-Pickers pick one and only one request, capture its index.
307 # from that point on this code *only* "listens" to that port.
309 sync
+= adrok_l
.s
.eq(0)
310 comb
+= adrok_l
.r
.eq(0)
311 with m
.If(~ldpick
.n
):
312 comb
+= ld_active
.s
.eq(1) # activate LD mode
313 comb
+= idx_l
.r
.eq(1) # pick (and capture) the port index
314 with m
.Elif(~stpick
.n
):
315 comb
+= st_active
.s
.eq(1) # activate ST mode
316 comb
+= idx_l
.r
.eq(1) # pick (and capture) the port index
318 # from this point onwards, with the port "picked", it stays picked
319 # until ld_active (or st_active) are de-asserted.
321 # if now in "LD" mode: wait for addr_ok, then send the address out
322 # to memory, acknowledge address, and send out LD data
323 with m
.If(ld_active
.q
):
324 with m
.If(ldport
.addr
.ok
& adrok_l
.qn
):
325 comb
+= rdport
.addr
.eq(ldport
.addr
.data
) # addr ok, send thru
326 comb
+= ldport
.addr_ok_o
.eq(1) # acknowledge addr ok
327 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
329 # if now in "ST" mode: likewise do the same but with "ST"
330 # to memory, acknowledge address, and send out LD data
331 with m
.If(st_active
.q
):
332 with m
.If(stport
.addr
.ok
):
333 comb
+= wrport
.addr
.eq(stport
.addr
.data
) # addr ok, send thru
334 with m
.If(adrok_l
.qn
):
335 comb
+= stport
.addr_ok_o
.eq(1) # acknowledge addr ok
336 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
338 # NOTE: in both these, below, the port itself takes care
339 # of de-asserting its "busy_o" signal, based on either ld.ok going
340 # high (by us, here) or by st.ok going high (by the LDSTCompUnit).
342 # for LD mode, when addr has been "ok'd", assume that (because this
343 # is a "Memory" test-class) the memory read data is valid.
344 comb
+= reset_l
.s
.eq(0)
345 comb
+= reset_l
.r
.eq(0)
346 with m
.If(ld_active
.q
& adrok_l
.q
):
347 comb
+= ldport
.ld
.data
.eq(rdport
.data
) # put data out
348 comb
+= ldport
.ld
.ok
.eq(1) # indicate data valid
349 comb
+= reset_l
.s
.eq(1) # reset mode after 1 cycle
351 # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
352 with m
.If(st_active
.q
& stport
.st
.ok
):
353 comb
+= wrport
.data
.eq(stport
.st
.data
) # write st to mem
354 comb
+= wrport
.en
.eq(1) # enable write
355 comb
+= reset_l
.s
.eq(1) # reset mode after 1 cycle
357 # after waiting one cycle (reset_l is "sync" mode), reset the port
358 with m
.If(reset_l
.q
):
359 comb
+= idx_l
.s
.eq(1) # deactivate port-index selector
360 comb
+= ld_active
.r
.eq(1) # leave the ST active for 1 cycle
361 comb
+= st_active
.r
.eq(1) # leave the ST active for 1 cycle
362 comb
+= reset_l
.r
.eq(1) # clear reset
363 comb
+= adrok_l
.r
.eq(1) # address reset
368 for p
in self
.dports
:
372 class TstL0CacheBuffer(Elaboratable
):
373 def __init__(self
, n_units
=3, regwid
=16, addrwid
=4):
374 self
.mem
= TestMemory(regwid
, addrwid
)
375 self
.l0
= L0CacheBuffer(n_units
, self
.mem
, regwid
, addrwid
)
377 def elaborate(self
, platform
):
379 m
.submodules
.mem
= self
.mem
380 m
.submodules
.l0
= self
.l0
385 yield from self
.l0
.ports()
386 yield self
.mem
.rdport
.addr
387 yield self
.mem
.rdport
.data
388 yield self
.mem
.wrport
.addr
389 yield self
.mem
.wrport
.data
393 def wait_busy(port
, no
=False):
395 busy
= yield port
.pi
.busy_o
396 print("busy", no
, busy
)
404 addr_ok
= yield port
.pi
.addr_ok_o
405 print("addrok", addr_ok
)
413 ldok
= yield port
.pi
.ld
.ok
420 def l0_cache_st(dut
, addr
, data
):
426 # have to wait until not busy
427 yield from wait_busy(port1
, no
=False) # wait until not busy
429 # set up a ST on the port. address first:
430 yield port1
.pi
.is_st_i
.eq(1) # indicate LD
432 yield port1
.pi
.addr
.data
.eq(addr
) # set address
433 yield port1
.pi
.addr
.ok
.eq(1) # set ok
434 yield from wait_addr(port1
) # wait until addr ok
435 # yield # not needed, just for checking
436 # yield # not needed, just for checking
437 # assert "ST" for one cycle (required by the API)
438 yield port1
.pi
.st
.data
.eq(data
)
439 yield port1
.pi
.st
.ok
.eq(1)
441 yield port1
.pi
.st
.ok
.eq(0)
443 # can go straight to reset.
444 yield port1
.pi
.is_st_i
.eq(0) # end
445 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
446 # yield from wait_busy(port1, False) # wait until not busy
449 def l0_cache_ld(dut
, addr
, expected
):
456 # have to wait until not busy
457 yield from wait_busy(port1
, no
=False) # wait until not busy
459 # set up a LD on the port. address first:
460 yield port1
.pi
.is_ld_i
.eq(1) # indicate LD
462 yield port1
.pi
.addr
.data
.eq(addr
) # set address
463 yield port1
.pi
.addr
.ok
.eq(1) # set ok
464 yield from wait_addr(port1
) # wait until addr ok
466 yield from wait_ldok(port1
) # wait until ld ok
467 data
= yield port1
.pi
.ld
.data
470 yield port1
.pi
.is_ld_i
.eq(0) # end
471 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
472 # yield from wait_busy(port1, no=False) # wait until not busy
477 def l0_cache_ldst(dut
):
483 yield from l0_cache_st(dut
, 0x2, data
)
484 yield from l0_cache_st(dut
, 0x3, data2
)
485 result
= yield from l0_cache_ld(dut
, 0x2, data
)
486 result2
= yield from l0_cache_ld(dut
, 0x3, data2
)
488 assert data
== result
, "data %x != %x" % (result
, data
)
489 assert data2
== result2
, "data2 %x != %x" % (result2
, data2
)
494 dut
= TstL0CacheBuffer()
495 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
496 with
open("test_basic_l0_cache.il", "w") as f
:
499 run_simulation(dut
, l0_cache_ldst(dut
),
500 vcd_name
='test_l0_cache_basic.vcd')
503 if __name__
== '__main__':