src/soc/experiment/l0_cache.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Mux, Elaboratable, Array
   4 from nmutil.iocontrol import RecordObject
   5
   6 from nmutil.latch import SRLatch, latchregister
   7 from soc.decoder.power_decoder2 import Data
   8 from soc.decoder.power_enums import InternalOp
   9
  10 from soc.experiment.compldst import CompLDSTOpSubset
  11 from soc.decoder.power_decode2 import Data
  12
  13
  14 class PortInterface(RecordObject):
  15
  16     def __init__(self, name=None):
  17
  18         RecordObject.__init__(self, name=name)
  19
  20         # distinguish op type (ld/st)
  21         self.is_ld_i = Signal(reset_less=True)
  22         self.is_st_i = Signal(reset_less=True)
  23         self.op = CompLDSTOpSubset() # hm insn_type ld/st duplicates here
  24
  25         # common signals
  26         self.busy_o = Signal(reset_less=True)     # do not use if busy
  27         self.go_die_i = Signal(reset_less=True)   # back to reset
  28         self.addr = Data(48, "addr_i")            # addr/addr-ok
  29         self.addr_ok_o = Signal(reset_less=True)  # addr is valid (TLB, L1 etc.)
  30         self.addr_exc_o = Signal(reset_less=True) # TODO, "type" of exception
  31
  32         # LD/ST
  33         self.ld = Data(64, "ld_data_o") # ok to be set by L0 Cache/Buf
  34         self.st = Data(64, "st_data_i") # ok to be set by CompUnit
  35
  36
  37 class L0CacheBuffer(Elaboratable):
  38     """L0 Cache / Buffer
  39
  40     Note that the final version will have *two* interfaces per LDSTCompUnit,
  41     to cover mis-aligned requests.
  42     """
  43
  44     def __init__(self, n_units):
  45         self.n_units = n_units
  46         ul = []
  47         for i in range(n_units):
  48             ul.append(PortInterface("ldst_port%d" % i))
  49         self.ports = Array(ul)
  50
  51
  52 def test_l0_cache():
  53     from alu_hier import ALU
  54
  55     alu = ALU(16)
  56     dut = ComputationUnitNoDelay(16, alu)
  57     vl = rtlil.convert(dut, ports=dut.ports())
  58     with open("test_compalu.il", "w") as f:
  59         f.write(vl)
  60
  61     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_compalu.vcd')
  62
  63
  64 if __name__ == '__main__':
  65     test_l0_cache()