src/soc/experiment/mem_types.py

   1 """mem_types
   2
   3 based on Anton Blanchard microwatt common.vhdl
   4
   5 """
   6 from nmutil.iocontrol import RecordObject
   7 from nmigen import Signal
   8
   9
  10 class DCacheToLoadStore1Type(RecordObject):
  11     def __init__(self, name=None):
  12         super().__init__(name=name)
  13         self.valid         = Signal()
  14         self.data          = Signal(64)
  15         self.store_done    = Signal()
  16         self.error         = Signal()
  17         self.cache_paradox = Signal()
  18
  19
  20 class DCacheToMMUType(RecordObject):
  21     def __init__(self, name=None):
  22         super().__init__(name=name)
  23         self.stall         = Signal()
  24         self.done          = Signal()
  25         self.err           = Signal()
  26         self.data          = Signal(64)
  27
  28
  29 class Fetch1ToICacheType(RecordObject):
  30     def __init__(self):
  31         super().__init__()
  32         self.req           = Signal()
  33         self.virt_mode     = Signal()
  34         self.priv_mode     = Signal()
  35         self.stop_mark     = Signal()
  36         self.sequential    = Signal()
  37         self.nia           = Signal(64)
  38
  39
  40 class ICacheToDecode1Type(RecordObject):
  41     def __init__(self):
  42         super().__init__()
  43         self.valid         = Signal()
  44         self.stop_mark     = Signal()
  45         self.fetch_failed  = Signal()
  46         self.nia           = Signal(64)
  47         self.insn          = Signal(32)
  48
  49
  50 class LoadStore1ToDCacheType(RecordObject):
  51     def __init__(self, name=None):
  52         super().__init__(name=name)
  53         self.valid         = Signal()
  54         self.load          = Signal() # this is a load
  55         self.dcbz          = Signal()
  56         self.nc            = Signal()
  57         self.nc            = Signal()
  58         self.reserve       = Signal()
  59         self.virt_mode     = Signal()
  60         self.priv_mode     = Signal()
  61         self.addr          = Signal(64)
  62         self.data          = Signal(64)
  63         self.byte_sel      = Signal(8)
  64
  65 class LoadStore1ToMMUType(RecordObject):
  66     def __init__(self):
  67         super().__init__()
  68         self.valid         = Signal()
  69         self.tlbie         = Signal()
  70         self.slbia         = Signal()
  71         self.mtspr         = Signal()
  72         self.iside         = Signal()
  73         self.load          = Signal()
  74         self.priv          = Signal()
  75         self.sprn          = Signal(10)
  76         self.addr          = Signal(64)
  77         self.rs            = Signal(64)
  78
  79
  80 class MMUToLoadStore1Type(RecordObject):
  81     def __init__(self):
  82         super().__init__()
  83         self.done          = Signal()
  84         self.err           = Signal()
  85         self.invalid       = Signal()
  86         self.badtree       = Signal()
  87         self.segerr        = Signal()
  88         self.perm_error    = Signal()
  89         self.rc_error      = Signal()
  90         self.sprval        = Signal(64)
  91
  92
  93 class MMUToDCacheType(RecordObject):
  94     def __init__(self, name=None):
  95         super().__init__(name=name)
  96         self.valid         = Signal()
  97         self.tlbie         = Signal()
  98         self.doall         = Signal()
  99         self.tlbld         = Signal()
 100         self.addr          = Signal(64)
 101         self.pte           = Signal(64)
 102
 103
 104 class MMUToICacheType(RecordObject):
 105     def __init__(self):
 106         super().__init__()
 107         self.tlbld         = Signal()
 108         self.tlbie         = Signal()
 109         self.doall         = Signal()
 110         self.addr          = Signal(64)
 111         self.pte           = Signal(64)
 112