3 based on Anton Blanchard microwatt common.vhdl
6 from nmutil
.iocontrol
import RecordObject
7 from nmigen
import Signal
9 # https://bugs.libre-soc.org/show_bug.cgi?id=465
10 class LDSTException(RecordObject
):
11 _exc_types
= ['alignment', 'instr_fault', 'invalid', 'badtree',
12 'perm_error', 'rc_error', 'segment_fault',]
13 def __init__(self
, name
=None):
14 RecordObject
.__init
__(self
, name
=name
)
15 self
.happened
= Signal()
16 for f
in self
._exc
_types
:
17 setattr(self
, f
, Signal())
20 class DCacheToLoadStore1Type(RecordObject
):
21 def __init__(self
, name
=None):
22 super().__init
__(name
=name
)
24 self
.data
= Signal(64)
25 self
.store_done
= Signal()
27 self
.cache_paradox
= Signal()
30 class DCacheToMMUType(RecordObject
):
31 def __init__(self
, name
=None):
32 super().__init
__(name
=name
)
36 self
.data
= Signal(64)
39 class Fetch1ToICacheType(RecordObject
):
40 def __init__(self
, name
=None):
41 super().__init
__(name
=name
)
43 self
.virt_mode
= Signal()
44 self
.priv_mode
= Signal()
45 self
.stop_mark
= Signal()
46 self
.sequential
= Signal()
50 class ICacheToDecode1Type(RecordObject
):
51 def __init__(self
, name
=None):
52 super().__init
__(name
=name
)
54 self
.stop_mark
= Signal()
55 self
.fetch_failed
= Signal()
57 self
.insn
= Signal(32)
60 class LoadStore1ToDCacheType(RecordObject
):
61 def __init__(self
, name
=None):
62 super().__init
__(name
=name
)
64 self
.load
= Signal() # this is a load
67 self
.reserve
= Signal()
68 self
.virt_mode
= Signal()
69 self
.priv_mode
= Signal()
70 self
.addr
= Signal(64)
71 self
.data
= Signal(64)
72 self
.byte_sel
= Signal(8)
75 class LoadStore1ToMMUType(RecordObject
):
76 def __init__(self
, name
=None):
77 super().__init
__(name
=name
)
85 self
.sprn
= Signal(10)
86 self
.addr
= Signal(64)
90 class MMUToLoadStore1Type(RecordObject
):
91 def __init__(self
, name
=None):
92 super().__init
__(name
=name
)
95 self
.invalid
= Signal()
96 self
.badtree
= Signal()
97 self
.segerr
= Signal()
98 self
.perm_error
= Signal()
99 self
.rc_error
= Signal()
100 self
.sprval
= Signal(64)
103 class MMUToDCacheType(RecordObject
):
104 def __init__(self
, name
=None):
105 super().__init
__(name
=name
)
106 self
.valid
= Signal()
107 self
.tlbie
= Signal()
108 self
.doall
= Signal()
109 self
.tlbld
= Signal()
110 self
.addr
= Signal(64)
111 self
.pte
= Signal(64)
114 class MMUToICacheType(RecordObject
):
115 def __init__(self
, name
=None):
116 super().__init
__(name
=name
)
117 self
.tlbld
= Signal()
118 self
.tlbie
= Signal()
119 self
.doall
= Signal()
120 self
.addr
= Signal(64)
121 self
.pte
= Signal(64)