src/soc/experiment/mem_types.py

   1 """mem_types
   2
   3 based on Anton Blanchard microwatt common.vhdl
   4
   5 """
   6 from nmutil.iocontrol import RecordObject
   7 from nmigen import Signal
   8
   9
  10 class DcacheToLoadStore1Type(RecordObject):
  11     def __init__(self):
  12         super().__init__()
  13         self.valid         = Signal()
  14         self.data          = Signal()
  15         self.store_done    = Signal()
  16         self.error         = Signal()
  17         self.cache_paradox = Signal()
  18
  19
  20 class DcacheToMmuType(RecordObject):
  21     def __init__(self):
  22         super().__init__()
  23         self.stall         = Signal()
  24         self.done          = Signal()
  25         self.err           = Signal()
  26         self.data          = Signal(64)
  27
  28 class LoadStore1ToDcacheType(RecordObject):
  29     def __init__(self):
  30         super().__init__()
  31         self.valid         = Signal()
  32         self.load          = Signal() # this is a load
  33         self.dcbz          = Signal()
  34         self.nc            = Signal()
  35         self.nc            = Signal()
  36         self.reserve       = Signal()
  37         self.virt_mode     = Signal()
  38         self.priv_mode     = Signal()
  39         self.addr          = Signal()
  40         self.data          = Signal()
  41         self.byte_sel      = Signal()
  42
  43 class LoadStore1ToMmuType(RecordObject):
  44     def __init__(self):
  45         super().__init__()
  46         self.valid         = Signal()
  47         self.tlbie         = Signal()
  48         self.slbia         = Signal()
  49         self.mtspr         = Signal()
  50         self.iside         = Signal()
  51         self.load          = Signal()
  52         self.priv          = Signal()
  53         self.sprn          = Signal(10)
  54         self.addr          = Signal(64)
  55         self.rs            = Signal(64)
  56
  57 class MmuToLoadStore1Type(RecordObject):
  58     def __init__(self):
  59         super().__init__()
  60         self.done          = Signal()
  61         self.err           = Signal()
  62         self.invalid       = Signal()
  63         self.badtree       = Signal()
  64         self.segerr        = Signal()
  65         self.perm_error    = Signal()
  66         self.rc_error      = Signal()
  67         self.sprval        = Signal(64)
  68
  69 class MmuToDcacheType(RecordObject):
  70     def __init__(self):
  71         super().__init__()
  72         self.valid         = Signal()
  73         self.tlbie         = Signal()
  74         self.doall         = Signal()
  75         self.tlbld         = Signal()
  76         self.addr          = Signal(64)
  77         self.pte           = Signal(64)
  78
  79 class MmuToIcacheType(RecordObject):
  80     def __init__(self):
  81         super().__init__()
  82         self.tlbld         = Signal()
  83         self.tlbie         = Signal()
  84         self.doall         = Signal()
  85         self.addr          = Signal(64)
  86         self.pte           = Signal(64)
  87