3 based on Anton Blanchard microwatt mmu.vhdl
6 from enum
import Enum
, unique
7 from nmigen
import (C
, Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
, Signal
)
8 from nmigen
.cli
import main
9 from nmigen
.cli
import rtlil
10 from nmutil
.iocontrol
import RecordObject
11 from nmutil
.byterev
import byte_reverse
12 from nmutil
.mask
import Mask
15 from soc
.experiment
.mem_types
import (LoadStore1ToMMUType
,
24 IDLE
= 0 # zero is default on reset for r.state
36 class RegStage(RecordObject
):
37 def __init__(self
, name
=None):
38 super().__init
__(name
=name
)
39 # latched request from loadstore1
44 self
.addr
= Signal(64)
45 self
.inval_all
= Signal()
47 self
.prtbl
= Signal(64)
50 self
.state
= Signal(State
) # resets to IDLE
53 self
.pgtbl0
= Signal(64)
54 self
.pt0_valid
= Signal()
55 self
.pgtbl3
= Signal(64)
56 self
.pt3_valid
= Signal()
57 self
.shift
= Signal(6)
58 self
.mask_size
= Signal(5)
59 self
.pgbase
= Signal(56)
61 self
.invalid
= Signal()
62 self
.badtree
= Signal()
63 self
.segerror
= Signal()
64 self
.perm_err
= Signal()
65 self
.rc_error
= Signal()
68 class MMU(Elaboratable
):
71 Supports 4-level trees as in arch 3.0B, but not the
72 two-step translation for guests under a hypervisor
73 (i.e. there is no gRA -> hRA translation).
76 self
.l_in
= LoadStore1ToMMUType()
77 self
.l_out
= MMUToLoadStore1Type()
78 self
.d_out
= MMUToDCacheType()
79 self
.d_in
= DCacheToMMUType()
80 self
.i_out
= MMUToICacheType()
82 def radix_tree_idle(self
, m
, l_in
, r
, v
):
86 with m
.If(~l_in
.addr
[63]):
87 comb
+= pgtbl
.eq(r
.pgtbl0
)
88 comb
+= pt_valid
.eq(r
.pt0_valid
)
90 comb
+= pgtbl
.eq(r
.pt3_valid
)
91 comb
+= pt_valid
.eq(r
.pt3_valid
)
93 # rts == radix tree size, number of address bits
96 comb
+= rts
.eq(Cat(pgtbl
[5:8], pgtbl
[61:63]))
98 # mbits == number of address bits to index top
101 comb
+= mbits
.eq(pgtbl
[0:5])
103 # set v.shift to rts so that we can use finalmask
104 # for the segment check
105 comb
+= v
.shift
.eq(rts
)
106 comb
+= v
.mask_size
.eq(mbits
[0:5])
107 comb
+= v
.pgbase
.eq(Cat(C(0, 8), pgtbl
[8:56]))
109 with m
.If(l_in
.valid
):
110 comb
+= v
.addr
.eq(l_in
.addr
)
111 comb
+= v
.iside
.eq(l_in
.iside
)
112 comb
+= v
.store
.eq(~
(l_in
.load | l_in
.iside
))
114 with m
.If(l_in
.tlbie
):
115 # Invalidate all iTLB/dTLB entries for
116 # tlbie with RB[IS] != 0 or RB[AP] != 0,
118 comb
+= v
.inval_all
.eq(l_in
.slbia
125 # The RIC field of the tlbie instruction
126 # comes across on the sprn bus as bits 2--3.
127 # RIC=2 flushes process table caches.
128 with m
.If(l_in
.sprn
[3]):
129 comb
+= v
.pt0_valid
.eq(0)
130 comb
+= v
.pt3_valid
.eq(0)
131 comb
+= v
.state
.eq(State
.DO_TLBIE
)
133 comb
+= v
.valid
.eq(1)
134 with m
.If(~pt_valid
):
135 # need to fetch process table entry
136 # set v.shift so we can use finalmask
137 # for generating the process table
139 comb
+= v
.shift
.eq(r
.prtbl
[0:5])
140 comb
+= v
.state
.eq(State
.PROC_TBL_READ
)
143 # Use RPDS = 0 to disable radix tree walks
144 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
145 comb
+= v
.invalid
.eq(1)
147 comb
+= v
.state
.eq(State
.SEGMENT_CHECK
)
149 with m
.If(l_in
.mtspr
):
150 # Move to PID needs to invalidate L1 TLBs
151 # and cached pgtbl0 value. Move to PRTBL
152 # does that plus invalidating the cached
153 # pgtbl3 value as well.
154 with m
.If(~l_in
.sprn
[9]):
155 comb
+= v
.pid
.eq(l_in
.rs
[0:32])
157 comb
+= v
.prtbl
.eq(l_in
.rs
)
158 comb
+= v
.pt3_valid
.eq(0)
160 comb
+= v
.pt0_valid
.eq(0)
161 comb
+= v
.inval_all
.eq(1)
162 comb
+= v
.state
.eq(State
.DO_TLBIE
)
164 def proc_tbl_wait(self
, m
, v
, r
, data
):
166 with m
.If(r
.addr
[63]):
167 comb
+= v
.pgtbl3
.eq(data
)
168 comb
+= v
.pt3_valid
.eq(1)
170 comb
+= v
.pgtbl0
.eq(data
)
171 comb
+= v
.pt0_valid
.eq(1)
172 # rts == radix tree size, # address bits being translated
174 comb
+= rts
.eq(Cat(data
[5:8], data
[61:63]))
176 # mbits == # address bits to index top level of tree
178 comb
+= mbits
.eq(data
[0:5])
179 # set v.shift to rts so that we can use
180 # finalmask for the segment check
181 comb
+= v
.shift
.eq(rts
)
182 comb
+= v
.mask_size
.eq(mbits
[0:5])
183 comb
+= v
.pgbase
.eq(Cat(C(0, 8), data
[8:56]))
186 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
187 comb
+= v
.invalid
.eq(1)
188 comb
+= v
.state
.eq(State
.SEGMENT_CHECK
)
190 def radix_read_wait(self
, m
, v
, r
, d_in
, data
):
192 comb
+= v
.pde
.eq(data
)
196 # check permissions and RC bits
198 comb
+= perm_ok
.eq(0)
199 with m
.If(r
.priv | ~data
[3]):
206 # no IAMR, so no KUEP support
207 # for now deny execute
208 # permission if cache inhibited
209 comb
+= perm_ok
.eq(data
[0] & ~data
[5])
212 comb
+= rc_ok
.eq(data
[8] & (data
[7] |
(~r
.store
)))
213 with m
.If(perm_ok
& rc_ok
):
214 comb
+= v
.state
.eq(State
.RADIX_LOAD_TLB
)
216 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
217 comb
+= v
.perm_err
.eq(~perm_ok
)
218 # permission error takes precedence
220 comb
+= v
.rc_error
.eq(perm_ok
)
223 comb
+= mbits
.eq(data
[0:5])
224 with m
.If((mbits
< 5) |
(mbits
> 16) |
(mbits
> r
.shift
)):
225 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
226 comb
+= v
.badtree
.eq(1)
228 comb
+= v
.shift
.eq(v
.shift
- mbits
)
229 comb
+= v
.mask_size
.eq(mbits
[0:5])
230 comb
+= v
.pgbase
.eq(Cat(C(0, 8), data
[8:56]))
231 comb
+= v
.state
.eq(State
.RADIX_LOOKUP
)
233 def segment_check(self
, m
, v
, r
, data
, finalmask
):
237 comb
+= mbits
.eq(r
.mask_size
)
238 comb
+= v
.shift
.eq(r
.shift
+ (31 - 12) - mbits
)
239 comb
+= nonzero
.eq((r
.addr
[31:62] & ~finalmask
[0:31]).bool())
240 with m
.If((r
.addr
[63] ^ r
.addr
[62]) | nonzero
):
241 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
242 comb
+= v
.segerror
.eq(1)
243 with m
.Elif((mbits
< 5) |
(mbits
> 16) |
244 (mbits
> (r
.shift
+ (31-12)))):
245 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
246 comb
+= v
.badtree
.eq(1)
248 comb
+= v
.state
.eq(State
.RADIX_LOOKUP
)
250 def elaborate(self
, platform
):
258 finalmask
= Signal(44)
261 rin
= RegStage("r_in")
269 # Multiplex internal SPR values back to loadstore1,
270 # selected by l_in.sprn.
271 with m
.If(l_in
.sprn
[9]):
272 comb
+= l_out
.sprval
.eq(r
.prtbl
)
274 comb
+= l_out
.sprval
.eq(r
.pid
)
276 with m
.If(rin
.valid
):
278 #sync += Display(f"MMU got tlb miss for {rin.addr}")
280 with m
.If(l_out
.done
):
282 # sync += Display("MMU completing op without error")
284 with m
.If(l_out
.err
):
286 # sync += Display(f"MMU completing op with err invalid"
287 # "{l_out.invalid} badtree={l_out.badtree}")
289 with m
.If(rin
.state
== State
.RADIX_LOOKUP
):
291 # sync += Display (f"radix lookup shift={rin.shift}"
292 # "msize={rin.mask_size}")
294 with m
.If(r
.state
== State
.RADIX_LOOKUP
):
296 # sync += Display(f"send load addr={d_out.addr}"
297 # "addrsh={addrsh} mask={mask}")
308 prtable_addr
= Signal(64)
309 pgtable_addr
= Signal(64)
311 tlb_data
= Signal(64)
315 comb
+= v
.valid
.eq(0)
319 comb
+= v
.invalid
.eq(0)
320 comb
+= v
.badtree
.eq(0)
321 comb
+= v
.segerror
.eq(0)
322 comb
+= v
.perm_err
.eq(0)
323 comb
+= v
.rc_error
.eq(0)
324 comb
+= tlb_load
.eq(0)
325 comb
+= itlb_load
.eq(0)
326 comb
+= tlbie_req
.eq(0)
327 comb
+= v
.inval_all
.eq(0)
328 comb
+= prtbl_rd
.eq(0)
330 # Radix tree data structures in memory are
331 # big-endian, so we need to byte-swap them
332 data
= byte_reverse(m
, "data", d_in
.data
, 8)
334 # generate mask for extracting address fields for PTE addr generation
335 m
.submodules
.pte_mask
= pte_mask
= Mask(16-5)
336 comb
+= pte_mask
.shift
.eq(r
.mask_size
- 5)
337 comb
+= mask
.eq(Cat(C(0x1f,5), pte_mask
.mask
))
339 # generate mask for extracting address bits to go in
340 # TLB entry in order to support pages > 4kB
341 m
.submodules
.tlb_mask
= tlb_mask
= Mask(44)
342 comb
+= tlb_mask
.shift
.eq(r
.shift
)
343 comb
+= finalmask
.eq(tlb_mask
.mask
)
345 with m
.Switch(r
.state
):
346 with m
.Case(State
.IDLE
):
347 self
.radix_tree_idle(m
, l_in
, r
, v
)
349 with m
.Case(State
.DO_TLBIE
):
351 comb
+= tlbie_req
.eq(1)
352 comb
+= v
.state
.eq(State
.TLB_WAIT
)
354 with m
.Case(State
.TLB_WAIT
):
355 with m
.If(d_in
.done
):
356 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
358 with m
.Case(State
.PROC_TBL_READ
):
360 comb
+= prtbl_rd
.eq(1)
361 comb
+= v
.state
.eq(State
.PROC_TBL_WAIT
)
363 with m
.Case(State
.PROC_TBL_WAIT
):
364 with m
.If(d_in
.done
):
365 self
.proc_tbl_wait(m
, v
, r
, data
)
368 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
369 comb
+= v
.badtree
.eq(1)
371 with m
.Case(State
.SEGMENT_CHECK
):
372 self
.segment_check(m
, v
, r
, data
, finalmask
)
374 with m
.Case(State
.RADIX_LOOKUP
):
376 comb
+= v
.state
.eq(State
.RADIX_READ_WAIT
)
378 with m
.Case(State
.RADIX_READ_WAIT
):
379 with m
.If(d_in
.done
):
380 self
.radix_read_wait(m
, v
, r
, d_in
, data
)
382 # non-present PTE, generate a DSI
383 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
384 comb
+= v
.invalid
.eq(1)
387 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
388 comb
+= v
.badtree
.eq(1)
390 with m
.Case(State
.RADIX_LOAD_TLB
):
391 comb
+= tlb_load
.eq(1)
394 comb
+= v
.state
.eq(State
.TLB_WAIT
)
396 comb
+= itlb_load
.eq(1)
397 comb
+= v
.state
.eq(State
.IDLE
)
399 with m
.Case(State
.RADIX_FINISH
):
400 comb
+= v
.state
.eq(State
.IDLE
)
402 with m
.If((v
.state
== State
.RADIX_FINISH
) |
403 ((v
.state
== State
.RADIX_LOAD_TLB
) & r
.iside
)):
404 comb
+= v
.err
.eq(v
.invalid | v
.badtree | v
.segerror
405 | v
.perm_err | v
.rc_error
)
406 comb
+= v
.done
.eq(~v
.err
)
408 with m
.If(~r
.addr
[63]):
409 comb
+= effpid
.eq(r
.pid
)
411 comb
+= prtable_addr
.eq(Cat(
414 (r
.prtbl
[12:36] & ~finalmask
[0:24]) |
415 (effpid
[8:32] & finalmask
[0:24]),
419 comb
+= pgtable_addr
.eq(Cat(
421 (r
.pgbase
[3:19] & ~mask
) |
428 (r
.pde
[12:56] & ~finalmask
) |
429 (r
.addr
[12:56] & finalmask
),
436 with m
.If(tlbie_req
):
437 comb
+= addr
.eq(r
.addr
)
438 with m
.Elif(tlb_load
):
439 comb
+= addr
.eq(Cat(C(0, 12), r
.addr
[12:64]))
440 comb
+= tlb_data
.eq(pte
)
441 with m
.Elif(prtbl_rd
):
442 comb
+= addr
.eq(prtable_addr
)
444 comb
+= addr
.eq(pgtable_addr
)
446 comb
+= l_out
.done
.eq(r
.done
)
447 comb
+= l_out
.err
.eq(r
.err
)
448 comb
+= l_out
.invalid
.eq(r
.invalid
)
449 comb
+= l_out
.badtree
.eq(r
.badtree
)
450 comb
+= l_out
.segerr
.eq(r
.segerror
)
451 comb
+= l_out
.perm_error
.eq(r
.perm_err
)
452 comb
+= l_out
.rc_error
.eq(r
.rc_error
)
454 comb
+= d_out
.valid
.eq(dcreq
)
455 comb
+= d_out
.tlbie
.eq(tlbie_req
)
456 comb
+= d_out
.doall
.eq(r
.inval_all
)
457 comb
+= d_out
.tlbld
.eq(tlb_load
)
458 comb
+= d_out
.addr
.eq(addr
)
459 comb
+= d_out
.pte
.eq(tlb_data
)
461 comb
+= i_out
.tlbld
.eq(itlb_load
)
462 comb
+= i_out
.tlbie
.eq(tlbie_req
)
463 comb
+= i_out
.doall
.eq(r
.inval_all
)
464 comb
+= i_out
.addr
.eq(addr
)
465 comb
+= i_out
.pte
.eq(tlb_data
)
472 yield wp
.data_i
.eq(2)
479 data
= yield rp
.data_o
488 yield wp
.data_i
.eq(6)
490 data
= yield rp
.data_o
497 data
= yield rp
.data_o
501 data
= yield rp
.data_o
506 vl
= rtlil
.convert(dut
, ports
=[])#dut.ports())
507 with
open("test_mmu.il", "w") as f
:
510 run_simulation(dut
, mmu_sim(), vcd_name
='test_mmu.vcd')
512 if __name__
== '__main__':