1 """PortInterface to LoadStoreUnitInterface adapter
3 PortInterface LoadStoreUnitInterface
4 ------------- ----------------------
9 data_len/4 x_mask/16 (translate using LenExpand)
11 busy_o/1 most likely to be x_busy_o
13 addr.data/48 x_addr_i (x_addr_i[:4] goes into LenExpand)
14 addr.ok/1 probably x_valid_i & ~x_stall_i
16 addr_ok_o/1 no equivalent. *might* work using x_stall_i
17 addr_exc_o/2(?) m_load_err_o and m_store_err_o
19 ld.data/64 m_ld_data_o
20 ld.ok/1 probably implicit, when x_busy drops low
21 st.data/64 x_st_data_i
22 st.ok/1 probably kinda redundant, set to x_st_i
25 from soc
.minerva
.units
.loadstore
import LoadStoreUnitInterface
26 from soc
.experiment
.pimem
import PortInterface
27 from soc
.scoreboard
.addr_match
import LenExpand
28 from soc
.experiment
.pimem
import PortInterfaceBase
29 from nmigen
.utils
import log2_int
31 from nmigen
import Elaboratable
, Module
, Signal
32 from nmutil
.latch
import SRLatch
33 from nmutil
.util
import rising_edge
37 class Pi2LSUI(PortInterfaceBase
):
39 def __init__(self
, name
, lsui
=None,
40 data_wid
=64, mask_wid
=8, addr_wid
=48):
41 print("pi2lsui reg mask addr", data_wid
, mask_wid
, addr_wid
)
42 super().__init
__(data_wid
, addr_wid
)
44 lsui
= LoadStoreUnitInterface(addr_wid
, self
.addrbits
, data_wid
)
46 self
.lsui_busy
= Signal()
47 self
.valid_l
= SRLatch(False, name
="valid")
49 def set_wr_addr(self
, m
, addr
, mask
):
50 m
.d
.comb
+= self
.valid_l
.s
.eq(1)
51 m
.d
.comb
+= self
.lsui
.x_mask_i
.eq(mask
)
52 m
.d
.comb
+= self
.lsui
.x_addr_i
.eq(addr
)
54 def set_rd_addr(self
, m
, addr
, mask
):
55 m
.d
.comb
+= self
.valid_l
.s
.eq(1)
56 m
.d
.comb
+= self
.lsui
.x_mask_i
.eq(mask
)
57 m
.d
.comb
+= self
.lsui
.x_addr_i
.eq(addr
)
59 def set_wr_data(self
, m
, data
, wen
): # mask already done in addr setup
60 m
.d
.comb
+= self
.lsui
.x_st_data_i
.eq(data
)
61 return (~
(self
.lsui
.x_busy_o | self
.lsui_busy
))
63 def get_rd_data(self
, m
):
64 return self
.lsui
.m_ld_data_o
, ~self
.lsui_busy
66 def elaborate(self
, platform
):
67 m
= super().elaborate(platform
)
68 pi
, lsui
, addrbits
= self
.pi
, self
.lsui
, self
.addrbits
70 m
.submodules
.valid_l
= self
.valid_l
71 ld_in_progress
= Signal()
73 # pass ld/st through to LSUI
74 m
.d
.comb
+= lsui
.x_ld_i
.eq(pi
.is_ld_i
)
75 m
.d
.comb
+= lsui
.x_st_i
.eq(pi
.is_st_i
)
77 # ooo how annoying. x_busy_o is set synchronously, i.e. one
78 # clock too late for this converter to "notice". consequently,
79 # when trying to wait for ld/st, here: on the first cycle
80 # it goes "oh, x_busy_o isn't set, the ld/st must have been
81 # completed already, we must be done" when in fact it hasn't
82 # started. to "fix" that we actually have to have a full FSM
83 # tracking from when LD/ST starts, right the way through. sigh.
84 # first clock busy signal. needed because x_busy_o is sync
87 # detect when ld/st starts. set busy *immediately*
88 with m
.If((pi
.is_ld_i | pi
.is_st_i
) & self
.valid_l
.q
):
89 m
.d
.comb
+= self
.lsui_busy
.eq(1)
92 # detect when busy drops: must then wait for ld/st to end..
93 #m.d.comb += self.lsui_busy.eq(self.lsui.x_busy_o)
94 m
.d
.comb
+= self
.lsui_busy
.eq(1)
95 with m
.If(~self
.lsui
.x_busy_o
):
96 m
.next
= "WAITDEASSERT"
97 with m
.State("WAITDEASSERT"):
98 # when no longer busy: back to start
99 with m
.If(~pi
.is_st_i
& ~pi
.busy_o
):
102 # indicate valid at both ends. OR with lsui_busy (stops comb loop)
103 m
.d
.comb
+= self
.lsui
.m_valid_i
.eq(self
.valid_l
.q
)
104 m
.d
.comb
+= self
.lsui
.x_valid_i
.eq(self
.valid_l
.q
)
106 # reset the valid latch when not busy. sync to stop loop
107 lsui_active
= Signal()
108 m
.d
.comb
+= lsui_active
.eq(~self
.lsui
.x_busy_o
)
109 m
.d
.comb
+= self
.valid_l
.r
.eq(rising_edge(m
, lsui_active
))
114 class Pi2LSUI1(Elaboratable
):
116 def __init__(self
, name
, pi
=None, lsui
=None,
117 data_wid
=64, mask_wid
=8, addr_wid
=48):
118 print("pi2lsui reg mask addr", data_wid
, mask_wid
, addr_wid
)
119 self
.addrbits
= mask_wid
121 piname
= "%s_pi" % name
122 pi
= PortInterface(piname
, regwid
=data_wid
, addrwid
=addr_wid
)
125 lsui
= LoadStoreUnitInterface(addr_wid
, self
.addrbits
, data_wid
)
128 def splitaddr(self
, addr
):
129 """split the address into top and bottom bits of the memory granularity
131 return addr
[:self
.addrbits
], addr
[self
.addrbits
:]
133 def connect_port(self
, inport
):
134 return self
.pi
.connect_port(inport
)
136 def elaborate(self
, platform
):
138 pi
, lsui
, addrbits
= self
.pi
, self
.lsui
, self
.addrbits
139 m
.submodules
.lenexp
= lenexp
= LenExpand(log2_int(self
.addrbits
), 8)
141 ld_in_progress
= Signal(reset
=0)
142 st_in_progress
= Signal(reset
=0)
144 m
.d
.comb
+= lsui
.x_ld_i
.eq(pi
.is_ld_i
)
145 m
.d
.comb
+= lsui
.x_st_i
.eq(pi
.is_st_i
)
146 m
.d
.comb
+= pi
.busy_o
.eq(pi
.is_ld_i | pi
.is_st_i
) # lsui.x_busy_o)
148 lsbaddr
, msbaddr
= self
.splitaddr(pi
.addr
.data
)
149 m
.d
.comb
+= lenexp
.len_i
.eq(pi
.data_len
)
150 m
.d
.comb
+= lenexp
.addr_i
.eq(lsbaddr
) # LSBs of addr
151 m
.d
.comb
+= lsui
.x_addr_i
.eq(pi
.addr
.data
) # XXX hmmm...
153 with m
.If(pi
.addr
.ok
):
154 # expand the LSBs of address plus LD/ST len into 16-bit mask
155 m
.d
.comb
+= lsui
.x_mask_i
.eq(lenexp
.lexp_o
)
156 # pass through the address, indicate "valid"
157 m
.d
.comb
+= lsui
.x_valid_i
.eq(1)
158 # indicate "OK" - XXX should be checking address valid
159 m
.d
.comb
+= pi
.addr_ok_o
.eq(1)
161 with m
.If(~lsui
.x_busy_o
& pi
.is_st_i
& pi
.addr
.ok
):
162 m
.d
.sync
+= st_in_progress
.eq(1)
164 with m
.If(pi
.is_ld_i
):
165 # shift/mask out the loaded data
166 m
.d
.comb
+= pi
.ld
.data
.eq((lsui
.m_ld_data_o
& lenexp
.rexp_o
) >>
168 # remember we're in the process of loading
169 with m
.If(pi
.addr
.ok
):
170 m
.d
.sync
+= ld_in_progress
.eq(1)
172 # If a load happened on the previous cycle and the memory is
173 # not busy, that means it returned the data from the load. In
174 # that case ld.ok should be set andwe can clear the
175 # ld_in_progress flag
176 with m
.If(ld_in_progress
& ~lsui
.x_busy_o
):
177 m
.d
.comb
+= pi
.ld
.ok
.eq(1)
178 m
.d
.sync
+= ld_in_progress
.eq(0)
180 m
.d
.comb
+= pi
.ld
.ok
.eq(0)
182 with m
.If(pi
.is_st_i
& pi
.st
.ok
):
183 m
.d
.comb
+= lsui
.x_st_data_i
.eq(pi
.st
.data
<< (lenexp
.addr_i
*8))
184 with m
.If(st_in_progress
):
185 m
.d
.sync
+= st_in_progress
.eq(0)
187 m
.d
.comb
+= pi
.busy_o
.eq(0)