1 """PortInterface to LoadStoreUnitInterface adapter
3 PortInterface LoadStoreUnitInterface
4 ------------- ----------------------
9 data_len/4 x_mask/16 (translate using LenExpand)
11 busy_o/1 most likely to be x_busy_o
13 addr.data/48 x_addr_i (x_addr_i[:4] goes into LenExpand)
14 addr.ok/1 probably x_valid_i & ~x_stall_i
16 addr_ok_o/1 no equivalent. *might* work using x_stall_i
17 addr_exc_o/2(?) m_load_err_o and m_store_err_o
19 ld.data/64 m_ld_data_o
20 ld.ok/1 probably implicit, when x_busy drops low
21 st.data/64 x_st_data_i
22 st.ok/1 probably kinda redundant, set to x_st_i
25 from soc
.minerva
.units
.loadstore
import LoadStoreUnitInterface
26 from soc
.experiment
.pimem
import PortInterface
27 from soc
.scoreboard
.addr_match
import LenExpand
28 from soc
.experiment
.pimem
import PortInterfaceBase
29 from nmigen
.utils
import log2_int
31 from nmigen
import Elaboratable
, Module
, Signal
32 from nmutil
.latch
import SRLatch
35 class Pi2LSUI(PortInterfaceBase
):
37 def __init__(self
, name
, lsui
=None,
38 data_wid
=64, mask_wid
=8, addr_wid
=48):
39 print("pi2lsui reg mask addr", data_wid
, mask_wid
, addr_wid
)
40 super().__init
__(data_wid
, addr_wid
)
42 lsui
= LoadStoreUnitInterface(addr_wid
, self
.addrbits
, data_wid
)
44 self
.lsui_busy
= Signal()
45 self
.valid_l
= SRLatch(False, name
="valid")
47 def set_wr_addr(self
, m
, addr
, mask
):
48 m
.d
.comb
+= self
.valid_l
.s
.eq(1)
49 m
.d
.comb
+= self
.lsui
.x_mask_i
.eq(mask
)
50 m
.d
.comb
+= self
.lsui
.x_addr_i
.eq(addr
)
52 def set_rd_addr(self
, m
, addr
, mask
):
53 m
.d
.comb
+= self
.valid_l
.s
.eq(1)
54 m
.d
.comb
+= self
.lsui
.x_mask_i
.eq(mask
)
55 m
.d
.comb
+= self
.lsui
.x_addr_i
.eq(addr
)
57 def set_wr_data(self
, m
, data
, wen
): # mask already done in addr setup
58 m
.d
.comb
+= self
.lsui
.x_st_data_i
.eq(data
)
59 return (~self
.lsui_busy
)
61 def get_rd_data(self
, m
):
62 return self
.lsui
.m_ld_data_o
, ~self
.lsui_busy
64 def elaborate(self
, platform
):
65 m
= super().elaborate(platform
)
66 pi
, lsui
, addrbits
= self
.pi
, self
.lsui
, self
.addrbits
68 m
.submodules
.valid_l
= self
.valid_l
69 ld_in_progress
= Signal()
71 # pass ld/st through to LSUI
72 m
.d
.comb
+= lsui
.x_ld_i
.eq(pi
.is_ld_i
)
73 m
.d
.comb
+= lsui
.x_st_i
.eq(pi
.is_st_i
)
75 # ooo how annoying. x_busy_o is set synchronously, i.e. one
76 # clock too late for this converter to "notice". consequently,
77 # when trying to wait for ld/st, here: on the first cycle
78 # it goes "oh, x_busy_o isn't set, the ld/st must have been
79 # completed already, we must be done" when in fact it hasn't
80 # started. to "fix" that we actually have to have a full FSM
81 # tracking from when LD/ST starts, right the way through. sigh.
82 # first clock busy signal. needed because x_busy_o is sync
85 # detect when ld/st starts. set busy *immediately*
86 with m
.If((pi
.is_ld_i | pi
.is_st_i
) & self
.valid_l
.q
):
87 m
.d
.comb
+= self
.lsui_busy
.eq(1)
90 # detect when busy drops: must then wait for ld/st to end..
91 #m.d.comb += self.lsui_busy.eq(self.lsui.x_busy_o)
92 m
.d
.comb
+= self
.lsui_busy
.eq(1)
93 with m
.If(~self
.lsui
.x_busy_o
):
94 m
.next
= "WAITDEASSERT"
95 with m
.State("WAITDEASSERT"):
96 # when no longer busy: back to start
97 with m
.If(~self
.valid_l
.q
):
100 # indicate valid at both ends
101 m
.d
.comb
+= self
.lsui
.m_valid_i
.eq(self
.valid_l
.q
)
102 m
.d
.comb
+= self
.lsui
.x_valid_i
.eq(self
.valid_l
.q
)
104 # reset the valid latch when not busy
105 m
.d
.comb
+= self
.valid_l
.r
.eq(~self
.lsui_busy
)#~pi.busy_o) # self.lsui.x_busy_o)
110 class Pi2LSUI1(Elaboratable
):
112 def __init__(self
, name
, pi
=None, lsui
=None,
113 data_wid
=64, mask_wid
=8, addr_wid
=48):
114 print("pi2lsui reg mask addr", data_wid
, mask_wid
, addr_wid
)
115 self
.addrbits
= mask_wid
117 piname
= "%s_pi" % name
118 pi
= PortInterface(piname
, regwid
=data_wid
, addrwid
=addr_wid
)
121 lsui
= LoadStoreUnitInterface(addr_wid
, self
.addrbits
, data_wid
)
124 def splitaddr(self
, addr
):
125 """split the address into top and bottom bits of the memory granularity
127 return addr
[:self
.addrbits
], addr
[self
.addrbits
:]
129 def connect_port(self
, inport
):
130 return self
.pi
.connect_port(inport
)
132 def elaborate(self
, platform
):
134 pi
, lsui
, addrbits
= self
.pi
, self
.lsui
, self
.addrbits
135 m
.submodules
.lenexp
= lenexp
= LenExpand(log2_int(self
.addrbits
), 8)
137 ld_in_progress
= Signal(reset
=0)
138 st_in_progress
= Signal(reset
=0)
140 m
.d
.comb
+= lsui
.x_ld_i
.eq(pi
.is_ld_i
)
141 m
.d
.comb
+= lsui
.x_st_i
.eq(pi
.is_st_i
)
142 m
.d
.comb
+= pi
.busy_o
.eq(pi
.is_ld_i | pi
.is_st_i
) # lsui.x_busy_o)
144 lsbaddr
, msbaddr
= self
.splitaddr(pi
.addr
.data
)
145 m
.d
.comb
+= lenexp
.len_i
.eq(pi
.data_len
)
146 m
.d
.comb
+= lenexp
.addr_i
.eq(lsbaddr
) # LSBs of addr
147 m
.d
.comb
+= lsui
.x_addr_i
.eq(pi
.addr
.data
) # XXX hmmm...
149 with m
.If(pi
.addr
.ok
):
150 # expand the LSBs of address plus LD/ST len into 16-bit mask
151 m
.d
.comb
+= lsui
.x_mask_i
.eq(lenexp
.lexp_o
)
152 # pass through the address, indicate "valid"
153 m
.d
.comb
+= lsui
.x_valid_i
.eq(1)
154 # indicate "OK" - XXX should be checking address valid
155 m
.d
.comb
+= pi
.addr_ok_o
.eq(1)
157 with m
.If(~lsui
.x_busy_o
& pi
.is_st_i
& pi
.addr
.ok
):
158 m
.d
.sync
+= st_in_progress
.eq(1)
160 with m
.If(pi
.is_ld_i
):
161 # shift/mask out the loaded data
162 m
.d
.comb
+= pi
.ld
.data
.eq((lsui
.m_ld_data_o
& lenexp
.rexp_o
) >>
164 # remember we're in the process of loading
165 with m
.If(pi
.addr
.ok
):
166 m
.d
.sync
+= ld_in_progress
.eq(1)
168 # If a load happened on the previous cycle and the memory is
169 # not busy, that means it returned the data from the load. In
170 # that case ld.ok should be set andwe can clear the
171 # ld_in_progress flag
172 with m
.If(ld_in_progress
& ~lsui
.x_busy_o
):
173 m
.d
.comb
+= pi
.ld
.ok
.eq(1)
174 m
.d
.sync
+= ld_in_progress
.eq(0)
176 m
.d
.comb
+= pi
.ld
.ok
.eq(0)
178 with m
.If(pi
.is_st_i
& pi
.st
.ok
):
179 m
.d
.comb
+= lsui
.x_st_data_i
.eq(pi
.st
.data
<< (lenexp
.addr_i
*8))
180 with m
.If(st_in_progress
):
181 m
.d
.sync
+= st_in_progress
.eq(0)
183 m
.d
.comb
+= pi
.busy_o
.eq(0)