1 from soc
.decoder
.power_enums
import InternalOp
3 from random
import randint
, seed
4 from copy
import deepcopy
9 def __init__(self
, regwid
, addrw
):
11 self
.ddepth
= 1 # regwid//8
12 depth
= (1<<addrw
) // self
.ddepth
13 self
.mem
= list(range(0, depth
))
16 return self
.mem
[addr
>>self
.ddepth
]
18 def st(self
, addr
, data
):
19 self
.mem
[addr
>>self
.ddepth
] = data
& ((1<<self
.regwid
)-1)
34 def __init__(self
, rwidth
, nregs
):
36 self
.regs
= [0] * nregs
38 def op(self
, op
, op_imm
, imm
, src1
, src2
, dest
):
39 print ("regsim op src1, src2", op
, op_imm
, imm
, src1
, src2
, dest
)
40 maxbits
= (1 << self
.rwidth
) - 1
41 src1
= self
.regs
[src1
] & maxbits
45 src2
= self
.regs
[src2
] & maxbits
46 if op
== InternalOp
.OP_ADD
:
48 elif op
== InternalOp
.OP_MUL_L64
:
50 print ("mul src1, src2", src1
, src2
, val
)
54 val
= src1
>> (src2
& maxbits
)
56 val
= int(src1
> src2
)
58 val
= int(src1
< src2
)
60 val
= int(src1
== src2
)
62 val
= int(src1
!= src2
)
66 self
.setval(dest
, val
)
69 def setval(self
, dest
, val
):
70 print ("sim setval", dest
, hex(val
))
74 for i
, val
in enumerate(self
.regs
):
75 reg
= yield dut
.intregs
.regs
[i
].reg
76 okstr
= "OK" if reg
== val
else "!ok"
77 print("reg %d expected %x received %x %s" % (i
, val
, reg
, okstr
))
80 for i
, val
in enumerate(self
.regs
):
81 reg
= yield dut
.intregs
.regs
[i
].reg
83 print("reg %d expected %x received %x\n" % (i
, val
, reg
))
84 yield from self
.dump(dut
)