1 from soc
.decoder
.power_enums
import MicrOp
3 from random
import randint
, seed
4 from copy
import deepcopy
9 def __init__(self
, regwid
, addrw
):
11 self
.ddepth
= 1 # regwid//8
12 depth
= (1 << addrw
) // self
.ddepth
13 self
.mem
= list(range(0, depth
))
16 return self
.mem
[addr
>> self
.ddepth
]
18 def st(self
, addr
, data
):
19 self
.mem
[addr
>> self
.ddepth
] = data
& ((1 << self
.regwid
)-1)
33 def __init__(self
, rwidth
, nregs
):
35 self
.regs
= [0] * nregs
37 def op(self
, op
, op_imm
, imm
, src1
, src2
, dest
):
38 print("regsim op src1, src2", op
, op_imm
, imm
, src1
, src2
, dest
)
39 maxbits
= (1 << self
.rwidth
) - 1
40 src1
= self
.regs
[src1
] & maxbits
44 src2
= self
.regs
[src2
] & maxbits
45 if op
== MicrOp
.OP_ADD
:
47 elif op
== MicrOp
.OP_MUL_L64
:
49 print("mul src1, src2", src1
, src2
, val
)
53 val
= src1
>> (src2
& maxbits
)
55 val
= int(src1
> src2
)
57 val
= int(src1
< src2
)
59 val
= int(src1
== src2
)
61 val
= int(src1
!= src2
)
65 self
.setval(dest
, val
)
68 def setval(self
, dest
, val
):
69 print("sim setval", dest
, hex(val
))
73 for i
, val
in enumerate(self
.regs
):
74 reg
= yield dut
.intregs
.regs
[i
].reg
75 okstr
= "OK" if reg
== val
else "!ok"
76 print("reg %d expected %x received %x %s" % (i
, val
, reg
, okstr
))
79 for i
, val
in enumerate(self
.regs
):
80 reg
= yield dut
.intregs
.regs
[i
].reg
82 print("reg %d expected %x received %x\n" % (i
, val
, reg
))
83 yield from self
.dump(dut
)