1 # test case for LOAD / STORE Computation Unit using MMU
3 #from nmigen.compat.sim import run_simulation
4 from nmigen
.compat
.sim
import Simulator
, Delay
, Settle
5 from nmigen
.cli
import verilog
, rtlil
6 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
7 from nmigen
.hdl
.rec
import Record
, Layout
9 from nmutil
.latch
import SRLatch
, latchregister
10 from nmutil
.byterev
import byte_reverse
11 from nmutil
.extend
import exts
12 from nmutil
.util
import wrap
13 from soc
.fu
.regspec
import RegSpecAPI
15 from openpower
.decoder
.power_enums
import MicrOp
, Function
, LDSTMode
16 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
17 from openpower
.decoder
.power_decoder2
import Data
18 from openpower
.consts
import MSR
20 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
21 from soc
.experiment
.l0_cache
import PortInterface
22 from soc
.experiment
.pimem
import LDSTException
23 from soc
.experiment
.compldst_multi
import LDSTCompUnit
, load
, store
24 from soc
.config
.test
.test_loadstore
import TestMemPspec
26 from soc
.experiment
.mmu
import MMU
27 from nmutil
.util
import Display
29 from soc
.config
.loadstore
import ConfigMemoryPortInterface
30 from soc
.experiment
.test
import pagetables
31 from soc
.experiment
.test
.test_wishbone
import wb_get
33 ########################################
35 # same thing as soc/src/soc/experiment/test/test_dcbz_pi.py
37 yield dut
.mmu
.rin
.prtbl
.eq(0x1000000) # set process table
39 data
= 0xf553b658ba7e1f51
41 yield from store(dut
, addr
, 0, data
, 0)
44 dut
.stop
= True # stop simulation
46 ########################################
49 class TestLDSTCompUnitMMU(LDSTCompUnit
):
51 def __init__(self
, rwid
, pspec
):
52 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
53 self
.l0
= l0
= TstL0CacheBuffer(pspec
)
55 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
57 def elaborate(self
, platform
):
58 m
= LDSTCompUnit
.elaborate(self
, platform
)
59 m
.submodules
.l0
= self
.l0
60 # link addr-go direct to rel
61 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
65 def test_scoreboard_mmu():
68 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
69 imem_ifacetype
='bare_wb',
75 dut
= TestLDSTCompUnitMMU(16,pspec
)
76 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
77 with
open("test_ldst_comp_mmu1.il", "w") as f
:
80 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
82 ########################################
83 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit
):
85 def __init__(self
, pspec
):
86 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
87 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
88 regspec
= LDSTPipeSpec
.regspec
90 # use a LoadStore1 here
92 cmpi
= ConfigMemoryPortInterface(pspec
)
98 LDSTCompUnit
.__init
__(self
, ldst
.pi
, regspec
, 4)
100 def elaborate(self
, platform
):
101 m
= LDSTCompUnit
.elaborate(self
, platform
)
102 m
.submodules
.l0
= self
.l0
103 m
.submodules
.mmu
= self
.mmu
104 # link addr-go direct to rel
105 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
107 # link mmu and dcache together
108 dcache
= self
.l0
.dcache
110 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
111 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
118 def test_scoreboard_regspec_mmu():
123 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
124 imem_ifacetype
='bare_wb',
130 dut
= TestLDSTCompUnitRegSpecMMU(pspec
)
132 m
.submodules
.dut
= dut
137 dut
.mem
= pagetables
.test1
140 sim
.add_sync_process(wrap(ldst_sim(dut
)))
141 sim
.add_sync_process(wrap(wb_get(dut
)))
142 with sim
.write_vcd('test_scoreboard_regspec_mmu'):
146 if __name__
== '__main__':
147 test_scoreboard_regspec_mmu()
148 #only one test for now -- test_scoreboard_mmu()