1 # test case for LOAD / STORE Computation Unit using MMU
3 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
, Tick
4 from nmigen
.cli
import verilog
, rtlil
5 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
6 from nmigen
.hdl
.rec
import Record
, Layout
8 from nmutil
.latch
import SRLatch
, latchregister
9 from nmutil
.byterev
import byte_reverse
10 from nmutil
.extend
import exts
11 from nmutil
.util
import wrap
12 from soc
.fu
.regspec
import RegSpecAPI
14 from openpower
.decoder
.power_enums
import MicrOp
, Function
, LDSTMode
15 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
16 from openpower
.decoder
.power_decoder2
import Data
17 from openpower
.consts
import MSR
19 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
20 from soc
.experiment
.l0_cache
import PortInterface
21 from soc
.experiment
.pimem
import LDSTException
22 from soc
.experiment
.compldst_multi
import LDSTCompUnit
, load
, store
23 from soc
.config
.test
.test_loadstore
import TestMemPspec
25 from soc
.experiment
.mmu
import MMU
26 from nmutil
.util
import Display
28 from soc
.config
.loadstore
import ConfigMemoryPortInterface
29 from soc
.experiment
.test
import pagetables
30 from soc
.experiment
.test
.test_wishbone
import wb_get
32 ########################################
34 def wait_for_debug(sig
, reason
, wait
=True, test1st
=False):
37 print("wait for", reason
, sig
, v
, wait
, test1st
)
38 if test1st
and bool(v
) == wait
:
43 raise(Exception(reason
))
47 #print("...wait for", sig, v)
51 def store_debug(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False,
52 byterev
=True,dcbz
=False):
53 print("cut here ======================================")
54 print("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
56 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_DCBZ
)
58 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_STORE
)
59 yield dut
.oper_i
.data_len
.eq(2) # half-word
60 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
61 yield dut
.src1_i
.eq(src1
)
62 yield dut
.src2_i
.eq(src2
)
63 yield dut
.src3_i
.eq(src3
)
64 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
65 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
66 #guess: this one was removed -- yield dut.oper_i.update.eq(update)
67 yield dut
.issue_i
.eq(1)
69 yield dut
.issue_i
.eq(0)
76 active_rel
= 0b001 # may be wrong, verify
78 # wait for all active rel signals to come up
81 rel
= yield dut
.rd
.rel_o
# guess: wrong in dcbz case
83 print("waitActiveRel",cnt
)
85 raise(Exception("Error1"))
86 print("rel EQ active_rel ?",rel
,active_rel
)
90 yield dut
.rd
.go_i
.eq(active_rel
)
92 yield dut
.rd
.go_i
.eq(0)
94 yield from wait_for_debug(dut
.adr_rel_o
, "addr valid",False, test1st
=True)
95 # yield from wait_for(dut.adr_rel_o)
96 # yield dut.ad.go.eq(1)
98 # yield dut.ad.go.eq(0)
101 yield from wait_for_debug(dut
.wr
.rel_o
[1],"update")
102 yield dut
.wr
.go
.eq(0b10)
104 addr
= yield dut
.addr_o
106 yield dut
.wr
.go
.eq(0)
109 print("not update ===============")
111 yield from wait_for_debug(dut
.sto_rel_o
,"sto_rel_o")
112 yield dut
.go_st_i
.eq(1)
114 yield dut
.go_st_i
.eq(0)
115 yield from wait_for_debug(dut
.busy_o
,"not_busy" ,False) #BUG: port interface stays busy until xxx
116 ###wait_for(dut.stwd_mem_o)
120 # same thing as soc/src/soc/experiment/test/test_dcbz_pi.py
122 yield dut
.mmu
.rin
.prtbl
.eq(0x1000000) # set process table
124 data
= 0xFF #just a single byte for this test
125 #data = 0xf553b658ba7e1f51
127 yield from store(dut
, addr
, 0, data
, 0)
129 ld_data
, data_ok
, ld_addr
= yield from load(dut
, addr
, 0, 0)
130 print(data
,data_ok
,ld_addr
)
131 assert(ld_data
==data
)
136 print("doing dcbz/store with data 0 .....")
137 yield from store_debug(dut
, addr
, 0, data
, 0, dcbz
=True) #hangs
139 ld_data
, data_ok
, ld_addr
= yield from load(dut
, addr
, 0, 0)
140 print(data
,data_ok
,ld_addr
)
143 assert(ld_data
==data
)
144 print("dzbz test passed")
146 dut
.stop
= True # stop simulation
148 ########################################
151 class TestLDSTCompUnitMMU(LDSTCompUnit
):
153 def __init__(self
, rwid
, pspec
):
154 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
155 self
.l0
= l0
= TstL0CacheBuffer(pspec
)
157 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
159 def elaborate(self
, platform
):
160 m
= LDSTCompUnit
.elaborate(self
, platform
)
161 m
.submodules
.l0
= self
.l0
162 # link addr-go direct to rel
163 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
167 def test_scoreboard_mmu():
170 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
171 imem_ifacetype
='bare_wb',
177 dut
= TestLDSTCompUnitMMU(16,pspec
)
178 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
179 with
open("test_ldst_comp_mmu1.il", "w") as f
:
182 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
184 ########################################
185 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit
):
187 def __init__(self
, pspec
):
188 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
189 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
190 regspec
= LDSTPipeSpec
.regspec
192 # use a LoadStore1 here
194 cmpi
= ConfigMemoryPortInterface(pspec
)
200 LDSTCompUnit
.__init
__(self
, ldst
.pi
, regspec
, 4)
202 def elaborate(self
, platform
):
203 m
= LDSTCompUnit
.elaborate(self
, platform
)
204 m
.submodules
.l0
= self
.l0
205 m
.submodules
.mmu
= self
.mmu
206 # link addr-go direct to rel
207 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
209 # link mmu and dcache together
210 dcache
= self
.l0
.dcache
212 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
213 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
220 def test_scoreboard_regspec_mmu():
225 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
226 imem_ifacetype
='bare_wb',
232 dut
= TestLDSTCompUnitRegSpecMMU(pspec
)
234 m
.submodules
.dut
= dut
239 dut
.mem
= pagetables
.test1
242 sim
.add_sync_process(wrap(ldst_sim(dut
)))
243 sim
.add_sync_process(wrap(wb_get(dut
)))
244 with sim
.write_vcd('test_scoreboard_regspec_mmu.vcd'):
248 if __name__
== '__main__':
249 test_scoreboard_regspec_mmu()
250 #only one test for now -- test_scoreboard_mmu()