1 # test case for LOAD / STORE Computation Unit using MMU
3 from nmigen
.sim
import Simulator
, Delay
, Settle
, Tick
4 from nmigen
.cli
import verilog
, rtlil
5 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
6 from nmigen
.hdl
.rec
import Record
, Layout
8 from nmutil
.latch
import SRLatch
, latchregister
9 from nmutil
.byterev
import byte_reverse
10 from nmutil
.extend
import exts
11 from nmutil
.util
import wrap
12 from soc
.fu
.regspec
import RegSpecAPI
14 from openpower
.decoder
.power_enums
import MicrOp
, Function
, LDSTMode
15 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
16 from openpower
.decoder
.power_decoder2
import Data
17 from openpower
.consts
import MSR
19 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
20 from soc
.experiment
.l0_cache
import PortInterface
21 from soc
.experiment
.pimem
import LDSTException
22 from soc
.experiment
.compldst_multi
import LDSTCompUnit
, load
, store
23 from soc
.config
.test
.test_loadstore
import TestMemPspec
25 from soc
.experiment
.mmu
import MMU
26 from nmutil
.util
import Display
28 from soc
.config
.loadstore
import ConfigMemoryPortInterface
29 from soc
.experiment
.test
import pagetables
30 from soc
.experiment
.test
.test_wishbone
import wb_get
32 ########################################
34 def wait_for_debug(sig
, reason
, wait
=True, test1st
=False):
37 print("wait for", reason
, sig
, v
, wait
, test1st
)
38 if test1st
and bool(v
) == wait
:
43 raise(Exception(reason
))
47 #print("...wait for", sig, v)
51 def store_debug(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False,
52 byterev
=True,dcbz
=False):
53 print("cut here ======================================")
54 print("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
56 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_DCBZ
)
58 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_STORE
)
59 yield dut
.oper_i
.data_len
.eq(2) # half-word
60 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
61 yield dut
.src1_i
.eq(src1
)
62 yield dut
.src2_i
.eq(src2
)
63 yield dut
.src3_i
.eq(src3
)
64 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
65 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
66 #guess: this one was removed -- yield dut.oper_i.update.eq(update)
67 yield dut
.issue_i
.eq(1)
69 yield dut
.issue_i
.eq(0)
76 active_rel
= 0b001 # may be wrong, verify
78 # wait for all active rel signals to come up
81 rel
= yield dut
.rd
.rel_o
# guess: wrong in dcbz case
83 print("waitActiveRel",cnt
)
85 raise(Exception("Error1"))
86 print("rel EQ active_rel ?",rel
,active_rel
)
90 yield dut
.rd
.go_i
.eq(active_rel
)
92 yield dut
.rd
.go_i
.eq(0)
94 yield from wait_for_debug(dut
.adr_rel_o
, "addr valid",False, test1st
=True)
95 # yield from wait_for(dut.adr_rel_o)
96 # yield dut.ad.go.eq(1)
98 # yield dut.ad.go.eq(0)
101 yield from wait_for_debug(dut
.wr
.rel_o
[1],"update")
102 yield dut
.wr
.go
.eq(0b10)
104 addr
= yield dut
.addr_o
106 yield dut
.wr
.go
.eq(0)
109 print("not update ===============")
111 yield from wait_for_debug(dut
.sto_rel_o
,"sto_rel_o")
112 yield dut
.go_st_i
.eq(1)
114 yield dut
.go_st_i
.eq(0)
115 yield from wait_for_debug(dut
.busy_o
,"not_busy" ,False)
116 ###wait_for(dut.stwd_mem_o)
120 # same thing as soc/src/soc/experiment/test/test_dcbz_pi.py
122 yield dut
.mmu
.rin
.prtbl
.eq(0x1000000) # set process table
124 data
= 0xFF #just a single byte for this test
125 #data = 0xf553b658ba7e1f51
127 yield from store(dut
, addr
, 0, data
, 0)
129 ld_data
, data_ok
, ld_addr
= yield from load(dut
, addr
, 0, 0)
130 print(data
,data_ok
,ld_addr
)
131 assert(ld_data
==data
)
136 print("doing dcbz/store with data 0 .....")
137 yield from store_debug(dut
, addr
, 0, data
, 0, dcbz
=True) #hangs
139 ld_data
, data_ok
, ld_addr
= yield from load(dut
, addr
, 0, 0)
140 print(data
,data_ok
,ld_addr
)
143 assert(ld_data
==data
)
144 print("dzbz test passed")
146 dut
.stop
= True # stop simulation
148 ########################################
149 class TestLDSTCompUnitMMU(LDSTCompUnit
):
151 def __init__(self
, rwid
, pspec
):
152 # use a LoadStore1 here
153 cmpi
= ConfigMemoryPortInterface(pspec
)
159 LDSTCompUnit
.__init
__(self
, ldst
.pi
, rwid
, 4)
161 def elaborate(self
, platform
):
162 m
= LDSTCompUnit
.elaborate(self
, platform
)
163 m
.submodules
.l0
= self
.l0
164 m
.submodules
.mmu
= self
.mmu
165 # link addr-go direct to rel
166 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
168 # link mmu and dcache together
169 dcache
= self
.l0
.dcache
171 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
172 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
177 def test_scoreboard_mmu():
182 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
183 imem_ifacetype
='bare_wb',
189 dut
= TestLDSTCompUnitMMU(16,pspec
)
191 m
.submodules
.dut
= dut
196 dut
.mem
= pagetables
.test1
199 sim
.add_sync_process(wrap(ldst_sim(dut
)))
200 sim
.add_sync_process(wrap(wb_get(dut
)))
201 with sim
.write_vcd('test_scoreboard_mmu.vcd'):
204 ########################################
205 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit
):
207 def __init__(self
, pspec
):
208 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
209 regspec
= LDSTPipeSpec
.regspec
211 # use a LoadStore1 here
212 cmpi
= ConfigMemoryPortInterface(pspec
)
218 LDSTCompUnit
.__init
__(self
, ldst
.pi
, regspec
, 4)
220 def elaborate(self
, platform
):
221 m
= LDSTCompUnit
.elaborate(self
, platform
)
222 m
.submodules
.l0
= self
.l0
223 m
.submodules
.mmu
= self
.mmu
224 # link addr-go direct to rel
225 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
227 # link mmu and dcache together
228 dcache
= self
.l0
.dcache
230 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
231 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
235 def test_scoreboard_regspec_mmu():
240 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
241 imem_ifacetype
='bare_wb',
247 dut
= TestLDSTCompUnitRegSpecMMU(pspec
)
249 m
.submodules
.dut
= dut
254 dut
.mem
= pagetables
.test1
257 sim
.add_sync_process(wrap(ldst_sim(dut
)))
258 sim
.add_sync_process(wrap(wb_get(dut
)))
259 with sim
.write_vcd('test_scoreboard_regspec_mmu.vcd'):
262 if __name__
== '__main__':
263 test_scoreboard_regspec_mmu()
264 test_scoreboard_mmu()