src/soc/experiment/test/test_dcbz_pi.py

   1 """DCache PortInterface Test
   2     starting as a copy to test_ldst_pi.py
   3 """
   4
   5 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
   6 from nmigen.cli import main
   7 from nmigen.cli import rtlil
   8 from nmutil.mask import Mask, masked
   9 from nmutil.util import Display
  10 from random import randint, seed
  11 from nmigen.sim import Simulator, Delay, Settle
  12 from nmutil.util import wrap
  13
  14 from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst, pi_dcbz
  15 from soc.config.test.test_loadstore import TestMemPspec
  16 from soc.config.loadstore import ConfigMemoryPortInterface
  17
  18 from soc.fu.ldst.loadstore import LoadStore1
  19 from soc.experiment.mmu import MMU
  20
  21 from nmigen.compat.sim import run_simulation
  22
  23
  24 stop = False
  25
  26 def b(x): # byte-reverse function
  27     return int.from_bytes(x.to_bytes(8, byteorder='little'),
  28                           byteorder='big', signed=False)
  29
  30 def wb_get(wb, mem):
  31     """simulator process for getting memory load requests
  32     """
  33
  34     global stop
  35     assert(stop==False)
  36
  37     while not stop:
  38         while True: # wait for dc_valid
  39             if stop:
  40                 return
  41             cyc = yield (wb.cyc)
  42             stb = yield (wb.stb)
  43             if cyc and stb:
  44                 break
  45             yield
  46         addr = (yield wb.adr) << 3
  47         if addr not in mem:
  48             print ("    WB LOOKUP NO entry @ %x, returning zero" % (addr))
  49
  50         # read or write?
  51         we = (yield wb.we)
  52         if we:
  53             store = (yield wb.dat_w)
  54             sel = (yield wb.sel)
  55             data = mem.get(addr, 0)
  56             # note we assume 8-bit sel, here
  57             res = 0
  58             for i in range(8):
  59                 mask = 0xff << (i*8)
  60                 if sel & (1<<i):
  61                     res |= store & mask
  62                 else:
  63                     res |= data & mask
  64             mem[addr] = res
  65             print ("    DCACHE set %x mask %x data %x" % (addr, sel, res))
  66         else:
  67             data = mem.get(addr, 0)
  68             yield wb.dat_r.eq(data)
  69             print ("    DCACHE get %x data %x" % (addr, data))
  70
  71         yield wb.ack.eq(1)
  72         yield
  73         yield wb.ack.eq(0)
  74         yield
  75
  76 def setup_mmu():
  77
  78     global stop
  79     stop = False
  80
  81     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  82                          imem_ifacetype='',
  83                          addr_wid=48,
  84                          #disable_cache=True, # hmmm...
  85                          mask_wid=8,
  86                          reg_wid=64)
  87
  88     m = Module()
  89     comb = m.d.comb
  90     cmpi = ConfigMemoryPortInterface(pspec)
  91     m.submodules.ldst = ldst = cmpi.pi
  92     m.submodules.mmu = mmu = MMU()
  93     dcache = ldst.dcache
  94
  95     l_in, l_out = mmu.l_in, mmu.l_out
  96     d_in, d_out = dcache.d_in, dcache.d_out
  97     wb_out, wb_in = dcache.wb_out, dcache.wb_in
  98
  99     # link mmu and dcache together
 100     m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 101     m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 102
 103     # link ldst and MMU together
 104     comb += l_in.eq(ldst.m_out)
 105     comb += ldst.m_in.eq(l_out)
 106
 107     return m, cmpi
 108
 109 ### test case for dcbz
 110
 111 def _test_dcbz_addr_100e0(dut, mem):
 112     mmu = dut.submodules.mmu
 113     pi = dut.submodules.ldst.pi
 114     global stop
 115     stop = False
 116
 117     yield mmu.rin.prtbl.eq(0x1000000) # set process table
 118     yield
 119
 120     addr = 0x100e0
 121     data = 0xf553b658ba7e1f51
 122
 123     yield from pi_st(pi, addr, data, 8, msr_pr=0)
 124     yield
 125
 126     ld_data = yield from pi_ld(pi, addr, 8, msr_pr=0)
 127     assert ld_data == 0xf553b658ba7e1f51
 128     ld_data = yield from pi_ld(pi, addr, 8, msr_pr=0)
 129     assert ld_data == 0xf553b658ba7e1f51
 130
 131     print("do_dcbz ===============")
 132     yield from pi_dcbz(pi, addr, msr_pr=0)
 133     print("done_dcbz ===============")
 134     yield
 135
 136     ld_data = yield from pi_ld(pi, addr, 8, msr_pr=0)
 137     print("ld_data after dcbz")
 138     print(ld_data)
 139     assert ld_data == 0
 140
 141     yield
 142     stop = True
 143
 144 def test_dcbz_addr_100e0():
 145
 146     m, cmpi = setup_mmu()
 147
 148     mem = {
 149            0x10000:    # PARTITION_TABLE_2
 150                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
 151            b(0x800000000100000b),
 152
 153            0x30000:     # RADIX_ROOT_PTE
 154                         # V = 1 L = 0 NLB = 0x400 NLS = 9
 155            b(0x8000000000040009),
 156
 157            0x40000:     # RADIX_SECOND_LEVEL
 158                         # V = 1 L = 1 SW = 0 RPN = 0
 159                         # R = 1 C = 1 ATT = 0 EAA 0x7
 160            b(0xc000000000000183),
 161
 162            0x1000000:   # PROCESS_TABLE_3
 163                         # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
 164            b(0x40000000000300ad),
 165
 166            0x10004: 0
 167
 168     }
 169
 170     # nmigen Simulation
 171     sim = Simulator(m)
 172     sim.add_clock(1e-6)
 173
 174     sim.add_sync_process(wrap(_test_dcbz_addr_100e0(m, mem)))
 175     sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
 176     with sim.write_vcd('test_dcbz_addr_zero.vcd'):
 177         sim.run()
 178
 179 if __name__ == '__main__':
 180     test_dcbz_addr_100e0()