2 test cases for LDSTSplitter and L0CacheBuffer2
5 from soc
.experiment
.l0_cache
import L0CacheBuffer2
6 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Cat
, Const
7 from nmigen
.cli
import rtlil
8 from soc
.scoreboard
.addr_split
import LDSTSplitter
9 from soc
.scoreboard
.addr_match
import LenExpand
11 from soc
.config
.test
.test_pi2ls
import pi_ld
, pi_st
, pi_ldst
13 from soc
.experiment
.pimem
import PortInterfaceBase
15 from nmigen
.compat
.sim
import run_simulation
, Settle
17 class TestCachedMemoryPortInterface(PortInterfaceBase
):
18 """TestCacheMemoryPortInterface
20 This is a test class for simple verification of LDSTSplitter
21 conforming to PortInterface
24 def __init__(self
, regwid
=64, addrwid
=4):
25 super().__init
__(regwid
, addrwid
)
26 self
.ldst
= LDSTSplitter(32, 48, 4)
28 def set_wr_addr(self
, m
, addr
, mask
):
29 m
.d
.comb
+= self
.ldst
.addr_i
.eq(addr
)
31 def set_rd_addr(self
, m
, addr
, mask
):
32 m
.d
.comb
+= self
.ldst
.addr_i
.eq(addr
)
34 def set_wr_data(self
, m
, data
, wen
):
35 m
.d
.comb
+= self
.ldst
.st_data_i
.data
.eq(data
) # write st to mem
36 m
.d
.comb
+= self
.ldst
.is_st_i
.eq(wen
) # enable writes
40 def get_rd_data(self
, m
):
41 # this path is still untested
43 return self
.ldst
.ld_data_o
.data
, ld_ok
45 def elaborate(self
, platform
):
46 m
= super().elaborate(platform
)
48 # add TestMemory as submodule
49 m
.submodules
.ldst
= self
.ldst
54 yield from super().ports()
57 def test_cache_single_run(dut
):
61 yield from pi_st(dut
.pi
, addr
, data
, 1)
63 def test_cache_single():
64 dut
= TestCachedMemoryPortInterface()
65 #LDSTSplitter(8, 48, 4) #data leng in bytes, address bits, select bits
67 run_simulation(dut
, test_cache_single_run(dut
),
68 vcd_name
='test_cache_single.vcd')
71 if __name__
== '__main__':