1 from nmigen
import (C
, Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
, Signal
)
2 from nmigen
.cli
import main
3 from nmigen
.cli
import rtlil
4 from nmutil
.mask
import Mask
, masked
5 from nmutil
.util
import Display
6 from random
import randint
, seed
7 from nmigen
.sim
import Simulator
, Delay
, Settle
8 from nmutil
.util
import wrap
10 from soc
.config
.test
.test_pi2ls
import pi_ld
, pi_st
, pi_ldst
, wait_busy
11 from soc
.config
.test
.test_loadstore
import TestMemPspec
12 from soc
.config
.loadstore
import ConfigMemoryPortInterface
14 from soc
.fu
.ldst
.loadstore
import LoadStore1
15 from soc
.experiment
.mmu
import MMU
16 from soc
.experiment
.test
import pagetables
18 from nmigen
.compat
.sim
import run_simulation
23 """simulator process for getting memory load requests
30 while True: # wait for dc_valid
38 addr
= (yield wb
.adr
) << 3
40 print (" WB LOOKUP NO entry @ %x, returning zero" % (addr
))
45 store
= (yield wb
.dat_w
)
47 data
= mem
.get(addr
, 0)
48 # note we assume 8-bit sel, here
57 print (" DCACHE set %x mask %x data %x" % (addr
, sel
, res
))
59 data
= mem
.get(addr
, 0)
60 yield wb
.dat_r
.eq(data
)
61 print (" DCACHE get %x data %x" % (addr
, data
))
73 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
76 #disable_cache=True, # hmmm...
82 cmpi
= ConfigMemoryPortInterface(pspec
)
83 m
.submodules
.ldst
= ldst
= cmpi
.pi
84 m
.submodules
.mmu
= mmu
= MMU()
87 l_in
, l_out
= mmu
.l_in
, mmu
.l_out
88 d_in
, d_out
= dcache
.d_in
, dcache
.d_out
89 wb_out
, wb_in
= dcache
.wb_out
, dcache
.wb_in
91 # link mmu and dcache together
92 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
93 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
95 # link ldst and MMU together
96 comb
+= l_in
.eq(ldst
.m_out
)
97 comb
+= ldst
.m_in
.eq(l_out
)
101 test_exceptions
= True
103 def _test_loadstore1(dut
, mem
):
104 mmu
= dut
.submodules
.mmu
105 pi
= dut
.submodules
.ldst
.pi
109 yield mmu
.rin
.prtbl
.eq(0x1000000) # set process table
113 data
= 0xf553b658ba7e1f51
115 yield from pi_st(pi
, addr
, data
, 8, msr_pr
=1)
118 ld_data
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
119 assert ld_data
== 0xf553b658ba7e1f51
120 ld_data
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
121 assert ld_data
== 0xf553b658ba7e1f51
123 print("do_dcbz ===============")
124 yield from pi_st(pi
, addr
, data
, 8, msr_pr
=1, is_dcbz
=1)
125 print("done_dcbz ===============")
128 ld_data
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
129 print("ld_data after dcbz")
134 # causes next test to hang
135 print("=== alignment error ===")
137 ld_data
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
138 alignment
= yield pi
.exc_o
.alignment
139 happened
= yield pi
.exc_o
.happened
144 yield from wait_busy(pi
, debug
="pi_ld_E_alignment_error")
145 # wait is only needed in case of in exception here
146 print("=== alignment error test passed ===")
149 ld_data
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
154 def test_loadstore1():
156 m
, cmpi
= setup_mmu()
158 mem
= pagetables
.test1
164 sim
.add_sync_process(wrap(_test_loadstore1(m
, mem
)))
165 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
166 with sim
.write_vcd('test_loadstore1.vcd'):
169 if __name__
== '__main__':