1 from nmigen
import (C
, Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
, Signal
)
2 from nmigen
.cli
import main
3 from nmigen
.cli
import rtlil
4 from nmutil
.mask
import Mask
, masked
5 from nmutil
.util
import Display
6 from random
import randint
, seed
7 from nmigen
.sim
import Simulator
, Delay
, Settle
8 from nmutil
.util
import wrap
10 from soc
.config
.test
.test_pi2ls
import pi_ld
, pi_st
, pi_ldst
, wait_busy
11 #from soc.config.test.test_pi2ls import pi_st_debug
12 from soc
.config
.test
.test_loadstore
import TestMemPspec
13 from soc
.config
.loadstore
import ConfigMemoryPortInterface
15 from soc
.fu
.ldst
.loadstore
import LoadStore1
16 from soc
.experiment
.mmu
import MMU
17 from soc
.experiment
.test
import pagetables
19 from nmigen
.compat
.sim
import run_simulation
24 """simulator process for getting memory load requests
31 while True: # wait for dc_valid
39 addr
= (yield wb
.adr
) << 3
41 print (" WB LOOKUP NO entry @ %x, returning zero" % (addr
))
46 store
= (yield wb
.dat_w
)
48 data
= mem
.get(addr
, 0)
49 # note we assume 8-bit sel, here
58 print (" DCACHE set %x mask %x data %x" % (addr
, sel
, res
))
60 data
= mem
.get(addr
, 0)
61 yield wb
.dat_r
.eq(data
)
62 print (" DCACHE get %x data %x" % (addr
, data
))
74 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
77 #disable_cache=True, # hmmm...
83 cmpi
= ConfigMemoryPortInterface(pspec
)
84 m
.submodules
.ldst
= ldst
= cmpi
.pi
85 m
.submodules
.mmu
= mmu
= MMU()
88 l_in
, l_out
= mmu
.l_in
, mmu
.l_out
89 d_in
, d_out
= dcache
.d_in
, dcache
.d_out
90 wb_out
, wb_in
= dcache
.wb_out
, dcache
.wb_in
92 # link mmu and dcache together
93 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
94 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
96 # link ldst and MMU together
97 comb
+= l_in
.eq(ldst
.m_out
)
98 comb
+= ldst
.m_in
.eq(l_out
)
102 test_exceptions
= True
104 def _test_loadstore1(dut
, mem
):
105 mmu
= dut
.submodules
.mmu
106 pi
= dut
.submodules
.ldst
.pi
110 yield mmu
.rin
.prtbl
.eq(0x1000000) # set process table
114 data
= 0xf553b658ba7e1f51
116 yield from pi_st(pi
, addr
, data
, 8, msr_pr
=1)
119 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
120 assert ld_data
== 0xf553b658ba7e1f51
122 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
123 assert ld_data
== 0xf553b658ba7e1f51
126 print("do_dcbz ===============")
127 yield from pi_st(pi
, addr
, data
, 8, msr_pr
=1, is_dcbz
=1)
128 print("done_dcbz ===============")
131 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
132 print("ld_data after dcbz")
138 print("=== alignment error (ld) ===")
140 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
141 alignment
= yield pi
.exc_o
.alignment
142 happened
= yield pi
.exc_o
.happened
148 yield from wait_busy(pi
, debug
="pi_ld_E_alignment_error")
149 # wait is only needed in case of in exception here
150 print("=== alignment error test passed (ld) ===")
152 print("=== alignment error (st) ===")
154 exc
= yield from pi_st(pi
, addr
,0, 8, msr_pr
=1)
155 alignment
= yield pi
.exc_o
.alignment
156 happened
= yield pi
.exc_o
.happened
162 yield from wait_busy(pi
, debug
="pi_st_E_alignment_error")
163 # wait is only needed in case of in exception here
164 print("=== alignment error test passed (st) ===")
165 yield # IMPORTANT: wait one clock cycle after failed st
167 print("=== no error ===")
169 ld_data
, exc
= yield from pi_ld(pi
, addr
, 8, msr_pr
=1)
170 print("ld_data",ld_data
,exc
)
171 print("=== no error done ===")
175 def test_loadstore1():
177 m
, cmpi
= setup_mmu()
179 mem
= pagetables
.test1
185 sim
.add_sync_process(wrap(_test_loadstore1(m
, mem
)))
186 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
187 with sim
.write_vcd('test_loadstore1.vcd'):
190 if __name__
== '__main__':