1 from nmigen
import (C
, Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
, Signal
,
3 from nmigen
.cli
import main
4 from nmigen
.cli
import rtlil
5 from nmutil
.mask
import Mask
, masked
6 from nmutil
.util
import Display
7 from random
import randint
, seed
8 from nmigen
.sim
import Simulator
, Delay
, Settle
9 from nmutil
.util
import wrap
11 from soc
.config
.test
.test_pi2ls
import (pi_ld
, pi_st
, pi_ldst
, wait_busy
,
13 #from soc.config.test.test_pi2ls import pi_st_debug
14 from soc
.config
.test
.test_loadstore
import TestMemPspec
15 from soc
.config
.loadstore
import ConfigMemoryPortInterface
17 from soc
.fu
.ldst
.loadstore
import LoadStore1
18 from soc
.experiment
.mmu
import MMU
19 from soc
.experiment
.test
import pagetables
21 from nmigen
.compat
.sim
import run_simulation
22 from random
import random
23 from openpower
.test
.wb_get
import wb_get
24 from openpower
.test
import wb_get
as wbget
25 from openpower
.exceptions
import LDSTExceptionTuple
27 from soc
.config
.test
.test_fetch
import read_from_addr
28 from openpower
.decoder
.power_enums
import MSRSpec
35 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
38 #disable_cache=True, # hmmm...
44 cmpi
= ConfigMemoryPortInterface(pspec
)
45 m
.submodules
.ldst
= ldst
= cmpi
.pi
46 m
.submodules
.mmu
= mmu
= MMU()
50 l_in
, l_out
= mmu
.l_in
, mmu
.l_out
51 d_in
, d_out
= dcache
.d_in
, dcache
.d_out
52 i_in
, i_out
= icache
.i_in
, icache
.i_out
# FetchToICache, ICacheToDecode
54 # link mmu, dcache and icache together
55 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
56 m
.d
.comb
+= icache
.m_in
.eq(mmu
.i_out
) # MMUToICacheType
57 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
59 # link ldst and MMU together
60 comb
+= l_in
.eq(ldst
.m_out
)
61 comb
+= ldst
.m_in
.eq(l_out
)
63 # add a debug status Signal: use "msg.str = "blah"
64 # then toggle with yield msg.eq(0); yield msg.eq(1)
65 debug_status
= Signal(8, decoder
=lambda _
: debug_status
.str)
66 m
.debug_status
= debug_status
72 def icache_read(dut
,addr
,priv
,virt
):
74 icache
= dut
.submodules
.ldst
.icache
78 yield i_in
.priv_mode
.eq(priv
)
79 yield i_in
.virt_mode
.eq(virt
)
81 yield i_in
.nia
.eq(addr
)
82 yield i_in
.stop_mark
.eq(0)
85 yield i_in
.nia
.eq(addr
)
87 valid
= yield i_out
.valid
88 failed
= yield i_out
.fetch_failed
89 while not valid
and not failed
:
91 valid
= yield i_out
.valid
92 failed
= yield i_out
.fetch_failed
96 insn
= yield i_out
.insn
100 return nia
, insn
, valid
, failed
103 test_exceptions
= True
109 print ("set debug message", msg
)
110 dut
.debug_status
.str = msg
# set the message
111 yield dut
.debug_status
.eq(0) # trigger an update
112 yield dut
.debug_status
.eq(1)
115 def _test_loadstore1_ifetch_iface(dut
, mem
):
116 """test_loadstore1_ifetch_iface
118 read in priv mode, non-virtual. tests the FetchUnitInterface
122 mmu
= dut
.submodules
.mmu
123 ldst
= dut
.submodules
.ldst
125 icache
= dut
.submodules
.ldst
.icache
128 print("=== test loadstore instruction (real) ===")
134 yield from debug(dut
, "real mem instruction")
135 # set address to 0x8, update mem[0x8] to 01234 | 0x5678<<32
136 # (have to do 64-bit writes into the dictionary-memory-emulated-thing)
139 expected_insn2
= 0x5678
140 expected_insn
= 0x1234
141 mem
[addr
] = expected_insn | expected_insn2
<<32
143 yield i_in
.priv_mode
.eq(1)
144 insn
= yield from read_from_addr(icache
, addr
, stall
=False)
146 nia
= yield i_out
.nia
# NO, must use FetchUnitInterface
147 print ("fetched %x from addr %x" % (insn
, nia
))
148 assert insn
== expected_insn
150 print("=== test loadstore instruction (2nd, real) ===")
151 yield from debug(dut
, "real mem 2nd (addr 0xc)")
153 insn2
= yield from read_from_addr(icache
, addr2
, stall
=False)
155 nia
= yield i_out
.nia
# NO, must use FetchUnitInterface
156 print ("fetched %x from addr2 %x" % (insn2
, nia
))
157 assert insn2
== expected_insn2
159 print("=== test loadstore instruction (done) ===")
161 yield from debug(dut
, "test done")
165 print ("fetched %x from addr %x" % (insn
, nia
))
166 assert insn
== expected_insn
171 def write_mem2(mem
, addr
, i1
, i2
):
172 mem
[addr
] = i1 | i2
<<32
175 #TODO: use fetch interface here
176 def lookup_virt(dut
,addr
):
177 icache
= dut
.submodules
.ldst
.icache
180 yield i_in
.priv_mode
.eq(0)
181 yield i_in
.virt_mode
.eq(1)
183 yield i_in
.stop_mark
.eq(0)
185 yield icache
.a_i_valid
.eq(1)
186 yield icache
.a_pc_i
.eq(addr
)
188 valid
= yield i_out
.valid
189 failed
= yield i_out
.fetch_failed
190 while not valid
and not failed
:
192 valid
= yield i_out
.valid
193 failed
= yield i_out
.fetch_failed
194 yield icache
.a_i_valid
.eq(0)
199 def mmu_lookup(dut
,addr
):
200 ldst
= dut
.submodules
.ldst
202 yield from debug(dut
, "instr fault "+hex(addr
))
203 yield ldst
.priv_mode
.eq(0)
204 yield ldst
.instr_fault
.eq(1)
205 yield ldst
.maddr
.eq(addr
)
207 yield ldst
.instr_fault
.eq(0)
209 done
= yield (ldst
.done
)
210 exc_info
= yield from get_exception_info(pi
.exc_o
)
211 if done
or exc_info
.happened
:
215 assert exc_info
.happened
== 0 # assert just before doing the fault set zero
216 yield ldst
.instr_fault
.eq(0)
217 yield from debug(dut
, "instr fault done "+hex(addr
))
223 def _test_loadstore1_ifetch_multi(dut
, mem
):
224 mmu
= dut
.submodules
.mmu
225 ldst
= dut
.submodules
.ldst
227 icache
= dut
.submodules
.ldst
.icache
228 assert wbget
.stop
== False
230 print ("set process table")
231 yield from debug(dut
, "set prtble")
232 yield mmu
.rin
.prtbl
.eq(0x1000000) # set process table
239 # fetch instructions from multiple addresses
240 # should cope with some addresses being invalid
241 real_addrs
= [0,4,8,0,8,4,0,0,12]
242 write_mem2(mem
,0,0xF0,0xF4)
243 write_mem2(mem
,8,0xF8,0xFC)
245 yield i_in
.priv_mode
.eq(1)
246 for addr
in real_addrs
:
247 yield from debug(dut
, "real_addr "+hex(addr
))
248 insn
= yield from read_from_addr(icache
, addr
, stall
=False)
249 nia
= yield i_out
.nia
# NO, must use FetchUnitInterface
250 print ("TEST_MULTI: fetched %x from addr %x == %x" % (insn
, nia
,addr
))
251 assert insn
==0xF0+addr
253 # now with virtual memory enabled
254 yield i_in
.virt_mode
.eq(1)
256 virt_addrs
= [0x10200,0x10204,0x10208,0x10200,
257 0x102008,0x10204,0x10200,0x10200,0x10200C]
259 write_mem2(mem
,0x10200,0xF8,0xFC)
261 for addr
in virt_addrs
:
262 yield from debug(dut
, "virt_addr "+hex(addr
))
264 valid
, failed
= yield from lookup_virt(dut
,addr
)
266 print("TEST_MULTI: failed=",failed
) # this is reported wrong
267 if failed
==1: # test one first
268 yield from mmu_lookup(dut
,addr
)
269 valid
, failed
= yield from lookup_virt(dut
,addr
)
275 def _test_loadstore1_ifetch(dut
, mem
):
276 """test_loadstore1_ifetch
278 this is quite a complex multi-step test.
280 * first (just because, as a demo) read in priv mode, non-virtual.
281 just like in experiment/icache.py itself.
283 * second, using the (usual) PTE for these things (which came originally
284 from gem5-experimental experiment/radix_walk_example.txt) do a
285 virtual-memory read through the *instruction* cache.
286 this is expected to FAIL
288 * third: mess about with the MMU, setting "iside" (instruction-side),
289 requesting an MMU RADIX LOOKUP. this triggers an itlb_load
290 (instruction-cache TLB entry-insertion)
292 * fourth and finally: retry the read of the instruction through i-cache.
293 this is now expected to SUCCEED
298 mmu
= dut
.submodules
.mmu
299 ldst
= dut
.submodules
.ldst
301 icache
= dut
.submodules
.ldst
.icache
304 print("=== test loadstore instruction (real) ===")
310 # first virtual memory test
312 print ("set process table")
313 yield from debug(dut
, "set prtble")
314 yield mmu
.rin
.prtbl
.eq(0x1000000) # set process table
317 yield from debug(dut
, "real mem instruction")
318 # set address to zero, update mem[0] to 01234
320 expected_insn
= 0x1234
321 mem
[addr
] = expected_insn
323 yield i_in
.priv_mode
.eq(1)
325 yield i_in
.nia
.eq(addr
)
326 yield i_in
.stop_mark
.eq(0)
327 yield i_m_in
.tlbld
.eq(0)
328 yield i_m_in
.tlbie
.eq(0)
329 yield i_m_in
.addr
.eq(0)
330 yield i_m_in
.pte
.eq(0)
335 # miss, stalls for a bit -- this one is different here
336 ##nia, insn, valid, failed = yield from icache_read(dut,addr,0,0)
341 yield i_in
.nia
.eq(addr
)
343 valid
= yield i_out
.valid
346 valid
= yield i_out
.valid
349 nia
= yield i_out
.nia
350 insn
= yield i_out
.insn
354 print ("fetched %x from addr %x" % (insn
, nia
))
355 assert insn
== expected_insn
357 print("=== test loadstore instruction (virtual) ===")
359 # look up i-cache expecting it to fail
361 yield from debug(dut
, "virtual instr req")
362 # set address to 0x10200, update mem[] to 5678
364 real_addr
= virt_addr
365 expected_insn
= 0x5678
366 mem
[real_addr
] = expected_insn
368 yield i_in
.priv_mode
.eq(0)
369 yield i_in
.virt_mode
.eq(1)
371 yield i_in
.nia
.eq(virt_addr
)
372 yield i_in
.stop_mark
.eq(0)
373 yield i_m_in
.tlbld
.eq(0)
374 yield i_m_in
.tlbie
.eq(0)
375 yield i_m_in
.addr
.eq(0)
376 yield i_m_in
.pte
.eq(0)
381 # miss, stalls for a bit
383 yield i_in
.nia
.eq(virt_addr
)
385 valid
= yield i_out
.valid
386 failed
= yield i_out
.fetch_failed
387 while not valid
and not failed
:
389 valid
= yield i_out
.valid
390 failed
= yield i_out
.fetch_failed
393 print ("failed?", "yes" if failed
else "no")
398 print("=== test loadstore instruction (instruction fault) ===")
400 yield from debug(dut
, "instr fault")
404 yield ldst
.priv_mode
.eq(0)
405 yield ldst
.instr_fault
.eq(1)
406 yield ldst
.maddr
.eq(virt_addr
)
407 # still broken -- investigate
408 # msr = MSRSpec(pr=?, dr=?, sf=0)
409 # ld_data, exctype, exc = yield from pi_ld(pi, virt_addr, 8, msr=msr)
411 yield ldst
.instr_fault
.eq(0)
413 done
= yield (ldst
.done
)
414 exc_info
= yield from get_exception_info(pi
.exc_o
)
415 if done
or exc_info
.happened
:
418 assert exc_info
.happened
== 0 # assert just before doing the fault set zero
419 yield ldst
.instr_fault
.eq(0)
424 print("=== test loadstore instruction (try instruction again) ===")
425 yield from debug(dut
, "instr virt retry")
426 # set address to 0x10200, update mem[] to 5678
428 real_addr
= virt_addr
429 expected_insn
= 0x5678
431 yield i_in
.priv_mode
.eq(0)
432 yield i_in
.virt_mode
.eq(1)
434 yield i_in
.nia
.eq(virt_addr
)
435 yield i_in
.stop_mark
.eq(0)
436 yield i_m_in
.tlbld
.eq(0)
437 yield i_m_in
.tlbie
.eq(0)
438 yield i_m_in
.addr
.eq(0)
439 yield i_m_in
.pte
.eq(0)
444 # miss, stalls for a bit
447 yield i_in.nia.eq(virt_addr)
449 valid = yield i_out.valid
450 failed = yield i_out.fetch_failed
451 while not valid and not failed:
453 valid = yield i_out.valid
454 failed = yield i_out.fetch_failed
456 nia = yield i_out.nia
457 insn = yield i_out.insn
461 nia
, insn
, valid
, failed
= yield from icache_read(dut
,virt_addr
,0,1)
463 yield from debug(dut
, "test done")
467 print ("failed?", "yes" if failed
else "no")
470 print ("fetched %x from addr %x" % (insn
, nia
))
471 assert insn
== expected_insn
476 def _test_loadstore1_invalid(dut
, mem
):
477 mmu
= dut
.submodules
.mmu
478 pi
= dut
.submodules
.ldst
.pi
481 print("=== test invalid ===")
484 msr
= MSRSpec(pr
=1, dr
=0, sf
=0) # set problem-state
485 ld_data
, exctype
, exc
= yield from pi_ld(pi
, addr
, 8, msr
=msr
)
486 print("ld_data", ld_data
, exctype
, exc
)
487 assert (exctype
== "slow")
488 invalid
= exc
.invalid
489 assert (invalid
== 1)
491 print("=== test invalid done ===")
496 def _test_loadstore1_microwatt_mmu_bin_test2(dut
, mem
):
497 mmu
= dut
.submodules
.mmu
498 pi
= dut
.submodules
.ldst
.pi
499 ldst
= dut
.submodules
.ldst
# to get at DAR (NOT part of PortInterface)
502 yield mmu
.rin
.prtbl
.eq(0x12000) # set process table
503 yield mmu
.rin
.pid
.eq(0x1) # set PID=1
507 msr
= MSRSpec(pr
=1, dr
=1, sf
=1)
509 print("=== alignment error (ld) ===")
511 ld_data
, exctype
, exc
= yield from pi_ld(pi
, addr
, 8, msr
=msr
)
512 print("ld_data after mmu.bin test2")
514 assert ld_data
== 0x0000000badc0ffee
515 assert exctype
is None
520 def test_pi_ld_misalign(pi
,addr
,data_len
,msr
):
521 for i
in range(0,data_len
):
522 ld_data
, exctype
, exc
= yield from pi_ld(pi
, addr
+i
, data_len
, msr
=msr
)
525 assert exc
is None # use "is None" not "== None"
526 print("MISALIGN: test_pi_ld_misalign returned",hex(ld_data
))
528 assert exc
.alignment
== 1
531 def _test_loadstore1_misalign(dut
, mem
):
532 mmu
= dut
.submodules
.mmu
533 pi
= dut
.submodules
.ldst
.pi
534 ldst
= dut
.submodules
.ldst
# to get at DAR (NOT part of PortInterface)
537 yield mmu
.rin
.prtbl
.eq(0x12000) # set process table
538 yield mmu
.rin
.pid
.eq(0x1) # set PID=1
542 msr
= MSRSpec(pr
=0, dr
=0, sf
=1)
544 yield from test_pi_ld_misalign(pi
,0,8,msr
)
549 def _test_loadstore1(dut
, mem
):
550 mmu
= dut
.submodules
.mmu
551 pi
= dut
.submodules
.ldst
.pi
552 ldst
= dut
.submodules
.ldst
# to get at DAR (NOT part of PortInterface)
555 yield mmu
.rin
.prtbl
.eq(0x1000000) # set process table
559 data
= 0xf553b658ba7e1f51
560 msr
= MSRSpec(pr
=0, dr
=0, sf
=0)
563 yield from pi_st(pi
, addr
, data
, 8, msr
=msr
)
566 ld_data
, exctype
, exc
= yield from pi_ld(pi
, addr
, 8, msr
=msr
)
567 assert ld_data
== 0xf553b658ba7e1f51
568 assert exctype
is None
570 ld_data
, exctype
, exc
= yield from pi_ld(pi
, addr
, 8, msr
=msr
)
571 assert ld_data
== 0xf553b658ba7e1f51
572 assert exctype
is None
574 print("do_dcbz ===============")
575 yield from pi_st(pi
, addr
, data
, 8, msr
=msr
, is_dcbz
=1)
576 print("done_dcbz ===============")
579 ld_data
, exctype
, exc
= yield from pi_ld(pi
, addr
, 8, msr
=msr
)
580 print("ld_data after dcbz")
583 assert exctype
is None
586 print("=== alignment error (ld) ===")
588 ld_data
, exctype
, exc
= yield from pi_ld(pi
, addr
, 8, msr
=msr
)
590 alignment
= exc
.alignment
591 happened
= exc
.happened
592 yield # wait for dsr to update
598 assert (happened
== 1)
599 assert (alignment
== 1)
601 assert (exctype
== "fast")
602 yield from wait_busy(pi
, debug
="pi_ld_E_alignment_error")
603 # wait is only needed in case of in exception here
604 print("=== alignment error test passed (ld) ===")
606 # take some cycles in between so that gtkwave separates out
613 print("=== alignment error (st) ===")
615 exctype
, exc
= yield from pi_st(pi
, addr
,0, 8, msr
=msr
)
617 alignment
= exc
.alignment
618 happened
= exc
.happened
622 assert (happened
== 1)
623 assert (alignment
==1)
625 assert (exctype
== "fast")
626 #???? yield from wait_busy(pi, debug="pi_st_E_alignment_error")
627 # wait is only needed in case of in exception here
628 print("=== alignment error test passed (st) ===")
632 print("=== no alignment error (ld) ===")
634 ld_data
, exctype
, exc
= yield from pi_ld(pi
, addr
, 8, msr
=msr
)
635 print("ld_data", ld_data
, exctype
, exc
)
637 alignment
= exc
.alignment
638 happened
= exc
.happened
642 assert (happened
== 0)
643 assert (alignment
== 0)
644 print("=== no alignment error done (ld) ===")
647 addrs
= [0x456920,0xa7a180,0x299420,0x1d9d60]
650 print("== RANDOM addr ==",hex(addr
))
651 ld_data
, exctype
, exc
= yield from pi_ld(pi
, addr
, 8, msr
=msr
)
652 print("ld_data[RANDOM]",ld_data
,exc
,addr
)
653 assert (exctype
== None)
656 print("== RANDOM addr ==",hex(addr
))
657 exc
= yield from pi_st(pi
, addr
,0xFF*addr
, 8, msr
=msr
)
658 assert (exctype
== None)
660 # readback written data and compare
662 print("== RANDOM addr ==",hex(addr
))
663 ld_data
, exctype
, exc
= yield from pi_ld(pi
, addr
, 8, msr
=msr
)
664 print("ld_data[RANDOM_READBACK]",ld_data
,exc
,addr
)
665 assert (exctype
== None)
666 assert (ld_data
== 0xFF*addr
)
668 print("== RANDOM addr done ==")
673 def _test_loadstore1_ifetch_invalid(dut
, mem
):
674 mmu
= dut
.submodules
.mmu
675 ldst
= dut
.submodules
.ldst
677 icache
= dut
.submodules
.ldst
.icache
680 print("=== test loadstore instruction (invalid) ===")
686 # first virtual memory test
688 print ("set process table")
689 yield from debug(dut
, "set prtbl")
690 yield mmu
.rin
.prtbl
.eq(0x1000000) # set process table
693 yield from debug(dut
, "real mem instruction")
694 # set address to zero, update mem[0] to 01234
696 expected_insn
= 0x1234
697 mem
[addr
] = expected_insn
699 yield i_in
.priv_mode
.eq(1)
701 yield i_in
.nia
.eq(addr
)
702 yield i_in
.stop_mark
.eq(0)
703 yield i_m_in
.tlbld
.eq(0)
704 yield i_m_in
.tlbie
.eq(0)
705 yield i_m_in
.addr
.eq(0)
706 yield i_m_in
.pte
.eq(0)
711 # miss, stalls for a bit
713 yield i_in
.nia
.eq(addr
)
715 valid
= yield i_out
.valid
716 nia
= yield i_out
.nia
719 valid
= yield i_out
.valid
722 nia
= yield i_out
.nia
723 insn
= yield i_out
.insn
728 print ("fetched %x from addr %x" % (insn
, nia
))
729 assert insn
== expected_insn
731 print("=== test loadstore instruction (virtual) ===")
732 yield from debug(dut
, "virtual instr req")
734 # look up i-cache expecting it to fail
736 # set address to 0x10200, update mem[] to 5678
738 real_addr
= virt_addr
739 expected_insn
= 0x5678
740 mem
[real_addr
] = expected_insn
742 yield i_in
.priv_mode
.eq(1)
743 yield i_in
.virt_mode
.eq(1)
745 yield i_in
.nia
.eq(virt_addr
)
746 yield i_in
.stop_mark
.eq(0)
747 yield i_m_in
.tlbld
.eq(0)
748 yield i_m_in
.tlbie
.eq(0)
749 yield i_m_in
.addr
.eq(0)
750 yield i_m_in
.pte
.eq(0)
755 # miss, stalls for a bit
757 yield i_in
.nia
.eq(virt_addr
)
759 valid
= yield i_out
.valid
760 failed
= yield i_out
.fetch_failed
761 while not valid
and not failed
:
763 valid
= yield i_out
.valid
764 failed
= yield i_out
.fetch_failed
767 print ("failed?", "yes" if failed
else "no")
772 print("=== test invalid loadstore instruction (instruction fault) ===")
774 yield from debug(dut
, "instr fault (perm err expected)")
777 yield ldst
.priv_mode
.eq(0)
778 yield ldst
.instr_fault
.eq(1)
779 yield ldst
.maddr
.eq(virt_addr
)
780 #ld_data, exctype, exc = yield from pi_ld(pi, virt_addr, 8, msr=msr)
782 yield ldst
.instr_fault
.eq(0)
784 done
= yield (ldst
.done
)
785 exc_info
= yield from get_exception_info(pi
.exc_o
)
786 if done
or exc_info
.happened
:
789 assert exc_info
.happened
== 1 # different here as expected
791 # TODO: work out what kind of exception occurred and check it's
792 # the right one. we *expect* it to be a permissions error because
793 # the RPTE leaf node in pagetables.test2 is marked as "non-executable"
794 # but we also expect instr_fault to be set because it is an instruction
796 print (" MMU lookup exception type?")
797 for fname
in LDSTExceptionTuple
._fields
:
798 print (" fname %20s %d" % (fname
, getattr(exc_info
, fname
)))
800 # ok now printed them out and visually inspected: check them with asserts
801 assert exc_info
.instr_fault
== 1 # instruction fault (yes!)
802 assert exc_info
.perm_error
== 1 # permissions (yes!)
803 assert exc_info
.rc_error
== 0
804 assert exc_info
.alignment
== 0
805 assert exc_info
.invalid
== 0
806 assert exc_info
.segment_fault
== 0
807 assert exc_info
.rc_error
== 0
809 yield from debug(dut
, "test done")
810 yield ldst
.instr_fault
.eq(0)
818 def test_loadstore1_ifetch_unit_iface():
820 m
, cmpi
= setup_mmu()
822 mem
= pagetables
.test1
824 # set this up before passing to Simulator (which calls elaborate)
825 icache
= m
.submodules
.ldst
.icache
826 icache
.use_fetch_interface() # this is the function which converts
827 # to FetchUnitInterface. *including*
828 # rewiring the Wishbone Bus to ibus
834 sim
.add_sync_process(wrap(_test_loadstore1_ifetch_iface(m
, mem
)))
835 # add two wb_get processes onto the *same* memory dictionary.
836 # this shouuuld work.... cross-fingers...
837 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
838 sim
.add_sync_process(wrap(wb_get(icache
.ibus
, mem
))) # ibus not bus
839 with sim
.write_vcd('test_loadstore1_ifetch_iface.vcd',
840 traces
=[m
.debug_status
]): # include extra debug
844 def test_loadstore1_ifetch():
846 m
, cmpi
= setup_mmu()
848 mem
= pagetables
.test1
854 icache
= m
.submodules
.ldst
.icache
855 sim
.add_sync_process(wrap(_test_loadstore1_ifetch(m
, mem
)))
856 # add two wb_get processes onto the *same* memory dictionary.
857 # this shouuuld work.... cross-fingers...
858 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
859 sim
.add_sync_process(wrap(wb_get(icache
.bus
, mem
)))
860 with sim
.write_vcd('test_loadstore1_ifetch.vcd',
861 traces
=[m
.debug_status
]): # include extra debug
865 def test_loadstore1():
867 m
, cmpi
= setup_mmu()
869 mem
= pagetables
.test1
875 sim
.add_sync_process(wrap(_test_loadstore1(m
, mem
)))
876 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
877 with sim
.write_vcd('test_loadstore1.vcd'):
881 def test_loadstore1_microwatt_mmu_bin_test2():
883 m
, cmpi
= setup_mmu()
885 mem
= pagetables
.microwatt_test2
891 sim
.add_sync_process(wrap(_test_loadstore1_microwatt_mmu_bin_test2(m
, mem
)))
892 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
893 with sim
.write_vcd('test_microwatt_mmu_test2.vcd'):
896 def test_loadstore1_misalign():
898 m
, cmpi
= setup_mmu()
900 mem
= pagetables
.microwatt_test2
906 ###########1122334455667788
907 mem
[0] = 0x0102030405060708
909 sim
.add_sync_process(wrap(_test_loadstore1_misalign(m
, mem
)))
910 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
911 with sim
.write_vcd('test_loadstore1_misalign.vcd'):
915 def test_loadstore1_invalid():
917 m
, cmpi
= setup_mmu()
925 sim
.add_sync_process(wrap(_test_loadstore1_invalid(m
, mem
)))
926 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
927 with sim
.write_vcd('test_loadstore1_invalid.vcd'):
931 def test_loadstore1_ifetch_invalid():
932 m
, cmpi
= setup_mmu()
934 # this is a specially-arranged page table which has the permissions
935 # barred for execute on the leaf node (EAA=0x2 instead of EAA=0x3)
936 mem
= pagetables
.test2
942 icache
= m
.submodules
.ldst
.icache
943 sim
.add_sync_process(wrap(_test_loadstore1_ifetch_invalid(m
, mem
)))
944 # add two wb_get processes onto the *same* memory dictionary.
945 # this shouuuld work.... cross-fingers...
946 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
947 sim
.add_sync_process(wrap(wb_get(icache
.bus
, mem
)))
948 with sim
.write_vcd('test_loadstore1_ifetch_invalid.vcd',
949 traces
=[m
.debug_status
]): # include extra debug
953 def test_loadstore1_ifetch_multi():
954 m
, cmpi
= setup_mmu()
957 # this is a specially-arranged page table which has the permissions
958 # barred for execute on the leaf node (EAA=0x2 instead of EAA=0x3)
959 mem
= pagetables
.test1
961 # set this up before passing to Simulator (which calls elaborate)
962 icache
= m
.submodules
.ldst
.icache
963 icache
.use_fetch_interface() # this is the function which converts
964 # to FetchUnitInterface. *including*
965 # rewiring the Wishbone Bus to ibus
971 sim
.add_sync_process(wrap(_test_loadstore1_ifetch_multi(m
, mem
)))
972 # add two wb_get processes onto the *same* memory dictionary.
973 # this shouuuld work.... cross-fingers...
974 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
975 sim
.add_sync_process(wrap(wb_get(icache
.ibus
, mem
))) # ibus not bus
976 with sim
.write_vcd('test_loadstore1_ifetch_multi.vcd',
977 traces
=[m
.debug_status
]): # include extra debug
980 if __name__
== '__main__':
982 test_loadstore1_microwatt_mmu_bin_test2()
983 #test_loadstore1_invalid()
984 #test_loadstore1_ifetch() #FIXME
985 #test_loadstore1_ifetch_invalid()
986 #test_loadstore1_ifetch_unit_iface() # guess: should be working
987 #test_loadstore1_ifetch_multi()
988 #test_loadstore1_misalign()