3 based on Anton Blanchard microwatt wishbone_types.vhdl
7 from nmigen
import Signal
8 from nmutil
.iocontrol
import RecordObject
12 # use ieee.std_logic_1164.all;
14 # package wishbone_types is
16 # -- Main CPU bus. 32-bit address, 64-bit data
18 # constant wishbone_addr_bits : integer := 32;
19 # constant wishbone_data_bits : integer := 64;
20 # constant wishbone_sel_bits : integer := wishbone_data_bits/8;
22 # Main CPU bus. 32-bit address, 64-bit data
25 WB_SEL_BITS
= WB_DATA_BITS
// 8
27 # subtype wishbone_addr_type is
28 # std_ulogic_vector(wishbone_addr_bits-1 downto 0);
29 # subtype wishbone_data_type is
30 # std_ulogic_vector(wishbone_data_bits-1 downto 0);
31 # subtype wishbone_sel_type is
32 # std_ulogic_vector(wishbone_sel_bits-1 downto 0);
35 return Signal(WB_ADDR_BITS
, name
="adr")
38 return Signal(WB_DATA_BITS
, name
="dat")
41 return Signal(WB_SEL_BITS
, name
="sel", reset
=0b11111111)
43 # type wishbone_master_out is record
44 # adr : wishbone_addr_type;
45 # dat : wishbone_data_type;
48 # sel : wishbone_sel_type;
51 class WBMasterOut(RecordObject
):
52 def __init__(self
, name
=None):
53 super().__init
__(name
=name
)
54 self
.adr
= WBAddrType()
55 self
.dat
= WBDataType()
58 self
.sel
= WBSelType()
61 # constant wishbone_master_out_init : wishbone_master_out := (
62 # adr => (others => '0'), dat => (others => '0'), cyc => '0',
63 # stb => '0', sel => (others => '0'), we => '0'
65 def WBMasterOutInit():
68 # type wishbone_slave_out is record
69 # dat : wishbone_data_type;
73 class WBSlaveOut(RecordObject
):
74 def __init__(self
, name
=None):
75 super().__init
__(name
=name
)
76 self
.dat
= WBDataType()
80 # constant wishbone_slave_out_init : wishbone_slave_out := (
81 # ack => '0', stall => '0', others => (others => '0')
86 # type wishbone_master_out_vector is array (natural range <>) of
87 # wishbone_master_out;
88 def WBMasterOutVector():
89 return Array(WBMasterOut())
91 # type wishbone_slave_out_vector is array (natural range <>) of
93 def WBSlaveOutVector():
94 return Array(WBSlaveOut())
96 # -- IO Bus to a device, 30-bit address, 32-bits data
97 # type wb_io_master_out is record
98 # adr : std_ulogic_vector(29 downto 0);
99 # dat : std_ulogic_vector(31 downto 0);
100 # sel : std_ulogic_vector(3 downto 0);
105 # IO Bus to a device, 30-bit address, 32-bits data
106 class WBIOMasterOut(RecordObject
):
107 def __init__(self
, name
=None):
108 super().__init
__(name
=name
)
109 self
.adr
= Signal(30)
110 self
.dat
= Signal(32)
116 # type wb_io_slave_out is record
117 # dat : std_ulogic_vector(31 downto 0);
119 # stall : std_ulogic;
121 class WBIOSlaveOut(RecordObject
):
122 def __init__(self
, name
=None):
123 super().__init
__(name
=name
)
124 self
.data
= Signal(32)
126 self
.stall
= Signal()
128 # constant wb_io_slave_out_init : wb_io_slave_out := (
129 # ack => '0', stall => '0', others => (others => '0')
131 def WBIOSlaveOutInit():
132 return WBIOSlaveOut()
134 # end package wishbone_types;